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| 型號(hào)： | ADT7462ACPZ-500RL7 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT |
| 封裝： | 5 X 5 MM, LFCSP-32 |
| 文件頁數(shù)： | 51/88頁 |
| 文件大?。?/td> | 836K |
| 代理商： | ADT7462ACPZ-500RL7 |
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ADT7462
Rev. 2 | Page 55 of 88 | www.onsemi.com
THERM I/O OPERATION
This section describes the operation of THERM1 and THERM2.
Pin 28 and Pin 29 can both be configured as THERM inputs or
outputs.
THERM OUTPUT
THERM is not enabled as an output by default on power-up, but
it can be enabled by setting the appropriate bits in Register 0x0E
(THERM1 configuration register) and Register 0x0F (THERM2
configuration register). THERM1 and THERM2 can be config-
ured to assert whenever a specific channel exceeds the specified
THERM limit (see Table 30).
Table 30. THERM Output Channel Select and Limits
Configuration
Limit Registers
Channel
Enable
THERM1,
Register 0x0E
THERM2,
Register 0x0F
THERM1
THERM2
Local
Bit 1 = 1
0x4C
0x50
Remote 1
Bit 2 = 1
0x4D
0x51
Remote 2
Bit 3 = 1
0x4E
0x52
Remote 3
Bit 4 = 1
0x4F
0x53
As an output, THERM is asserted low to signal that the measured
THERM temperature has exceeded preprogrammed THERM
temperature limits. The output is automatically pulled high again
when the temperature falls below the (THERM Hysteresis) limit.
The value of hysteresis for each channel is programmable in
Register 0x54 and Register 0x55, where 1 LSB = 1°C, and the
maximum hysteresis for each channel is 15°C.
Setting the THERM boost bits, Bit 0 and Bit 1, to Logic 0
(default setting) in the THERM configuration register (0x0D),
sets the fans to full speed on an internal THERM event.
THERM INPUT
To configure THERM as an input, the THERM1_Timer_Enable
(T1TE) bit (Bit 0) in the THERM1 configuration register (0x0E)
and the THERM2_Timer_Enable (T2TE) bit (Bit 0) in the
THERM2 configuration register (0x0F) must be set to Logic 1.
The ADT7462 can then be used to detect when the THERM
pins are asserted low. The THERM pins can be connected to a
trip point temperature sensor or to the PROCHOT output of a
CPU.
With processor core voltages reducing all the time, the threshold
for the AGTL+ PROCHOT output is also reduced as new
processors become available.
Because the THERM input is typically an AGTL+ input, the
thresholds can be referenced to VCCP. By setting Bit 4 of
Configuration Register 3 (0x03) to 1, the THERM threshold is
2/3 × VCCP, the correct threshold for an AGTL+ signal. The
THERM assert bits in Host Thermal Status Register 2 (0xB9)
are set to Logic 1 whenever the THERM input is asserted low.
The THERM state bits in Host Thermal Status Register 2 (0xB9)
indicate that a high-to-low transition has taken place on the
THERM pin.
100°C
90°C
80°C
70°C
60°C
50°C
40°C
THERM
THERM LIMIT
THERM LIMIT–HYSTERESIS
TEMPERATURE
HIGH TEMP LIMIT
1
3
2
4
RESET BY MASTER
ALERT
055
69-
07
3
Figure 84. THERM Behavior
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