參數(shù)資料
型號(hào)： ADT7462ACPZ-500RL7
廠商： ON SEMICONDUCTOR
元件分類(lèi)： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, LFCSP-32
文件頁(yè)數(shù)： 22/88頁(yè)
文件大?。?/td> 836K
代理商： ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 29 of 88 | www.onsemi.com
DYNAMIC VID FUNCTIONALITY
VID CODE
The ADT7462 can be configured to monitor up to seven VID
inputs. The VID code is output on seven lines from the CPU to tell
the power controller what input voltage it requires. The ADT7462
can monitor the VID code and the voltage applied to the CPU to
ensure that they match within an acceptable range. This acceptable
range is programmable in the ADT7462.
The VID lines are monitored by the ADT7462, and the VID code is
stored in the VID Value register (0x97), which can be read back over
the SMBus.
VID monitoring is enabled by setting Bit 7 (VIDs) of Pin
Configuration Register 1 (0x10) to 1. See Table 21 and Table 22 for
information on which pin should be connected to each VID line.
When VID monitoring is enabled, all seven pins are automatically
configured as VID inputs. It is not possible to select six pins as VID
inputs and use the remaining pin as an alternate function.
VID Value Register (0x97)
Bit 0 = VID0 (reflects the logic state of Pin 1)
Bit 1 = VID1 (reflects the logic state of Pin 2)
Bit 2 = VID2 (reflects the logic state of Pin 3)
Bit 3 = VID3 (reflects the logic state of Pin 4)
Bit 4 = VID4 (reflects the logic state of Pin 31)
Bit 5 = VID5 (reflects the logic state of Pin 32)
Bit 6 = VID6 (reflects the logic state of Pin 28)
The ADT7462 supports both the VR10 and the VR11 specifications.
The default option supports the VR10 specification. To switch to the
VR11 specification, set Bit 6 of Configuration Register 0 (0x00) to 1.
VR11 is defined as eight bits; the ADT7462 monitors only seven
VID lines (see Table 21).
Table 21. VR11 VID Codes
VID Number
Pin No.
Voltage
VID6
28
400 mV
VID5
32
200 mV
VID4
31
100 mV
VID3
4
50 mV
VID2
3
25 mV
VID1
2
12.5 mV
VID0
1
6.25 mV
VR10 requires only six VID lines (see Table 22). Pin 28 should be
connected to ground when monitoring VR10 VID codes. VID6
reports a 0.
Table 22. VR10 VID Codes
VID Number
Pin No.
Voltage
VID6
28
Unused, connect to GND
VID5
32
12.5 mV
VID4
31
400 mV
VID3
4
200 mV
VID2
3
100 mV
VID1
2
60 mV
VID0
1
25 mV
DYNAMIC VID MONITORING
The ADT7462 supports dynamic VID monitoring. The purpose
of the VID code is to tell the voltage controller what VCCP
voltage should be applied to the CPU. The VCCP voltage applied
to the processor changes as the power requirements of the
processor change. The VID is compared with VCCP1 only. Note
that when the VIDs are enabled, the LSB value for VCCP1
becomes 0.0125 V (see Table 16).
The VID values can represent voltages from 0.8375 V to 1.6 V.
The VID code is sampled by the ADT7462 every 11 μs and is
stored in Register 0x97. Once the VID code has been stable
(that is, does not change) for 55 μs, the measured VCCP is then
compared with the VID code. The comparison table used is
for either the VR10 or the VR11 specification (set by Bit 6 of
Register 0x00). If the VID code and the measured VCCP do not
match within a certain limit, an ALERT is generated.
The VID value decoded and the VCCP measurement must be
within a window controlled by the VID high and low limits.
The VID is compared with VCCP1 only. Register 0x78 holds the
4-bit VID high and low limits. The high limit has a range of
0 mV to 375 mV with a resolution of 25 mV (four bits). The low
limit has a range of 0 mV to 187.5 mV with a resolution of
12.5 mV (four bits). The high limit is used in a greater-than
comparison, and the low limit is used in a less-than-or-equal-to
comparison. Note that if both limits are set to 0x00, because the
low limit is less than or equal to the comparison, an ALERT
always results. Therefore, the minimum value for low limit is 0x01.
If the VCCP voltage measured and the VID code do not match to
within the programmed limit, Status Bit 6 of the digital status
register is set (Register 0xBE). This, in turn, can generate an
ALERT if it is not masked.
Example
VID high limit: 100 mV (Register 0x78), four MSBs set to 0100.
VID low limit: 50 mV (Register 0x78), four LSBs set to 0100.
VID value equates to 1.1 V. This is the read VID decoded, using
either VR10 or VR11 tables.
VCCP1 must be in the window of 1.05 V to 1.2 V. If the VCCP1 value
is outside this window, the status bit is set and an ALERT is
generated.
To clear an ALERT generated in this way, read the digital status
register. If the VID code and VCCP are now matching within the
programmed window (that is, the error condition that caused the
ALERT has gone away), then the status bit is reset and so is the
ALERT.
The VID to VCCP voltage tables for both VR10 and VR11 can be
found on the Intel website. See the Voltage Regulator Module
(VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design
Guidelines, Page 18 and Page 19, for additional information.
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