參數(shù)資料
型號： ADT7462ACPZ-500RL7
廠商： ON SEMICONDUCTOR
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, LFCSP-32
文件頁數(shù)： 35/88頁
文件大?。?/td> 836K
代理商： ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 40 of 88 | www.onsemi.com
STEP 3—PWMMIN FOR EACH PWM (FAN) OUTPUT
PWMMIN is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control when the temperature rises above TMIN.
For maximum system acoustic benefit, PWMMIN should be as
low as possible. Depending on the fan used, the PWMMIN
setting is usually in the 20% to 33% duty cycle range. This value
can be found through fan validation.
TEMPERATURE
TMIN
100%
PWMMIN
0%
P
W
M
DUT
Y
CY
CL
E
055
69-
043
Figure 55. PWMMIN Determines Minimum PWM Duty Cycle at TMIN
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, the fan characteris-
tics can be set up differently. As a result, Fan 1, driven by
PWM1, can have a different PWMMIN value than that of Fan 2
connected to PWM2. Figure 56 illustrates this as PWM1MIN (the
front fan) turns on at a minimum duty cycle of 20%, while
PWM2MIN (the rear fan) turns on at a minimum duty cycle of
40%. Note, however, that both fans turn on at exactly the same
temperature, defined by TMIN.
TEMPERATURE
TMIN
100%
PWM1MIN
0%
PW
M
DU
T
Y
C
Y
CL
E
PW
M1
PW
M2
PWM2MIN
05569
-0
44
Figure 56. Operating Two Different Fans from a Single Temperature Channel
Programming the PWMMIN Registers
The PWMMIN registers are 8-bit registers that allow the
minimum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWMMIN register is given by
Value (decimal) = PWMMIN/0.39
Example 1
For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hexadecimal)
Example 2
For a minimum PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hexadecimal)
PWMMIN Registers
Register 0x28, Minimum PWM1 Duty Cycle = 0x80 (50% default)
Register 0x29, Minimum PWM2 Duty Cycle = 0x80 (50% default)
Register 0x2A, Minimum PWM3 Duty Cycle = 0x80 (50% default)
Register 0x2B, Minimum PWM4 Duty Cycle = 0x80 (50% default)
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in
rpm. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in % rpm generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in rpm approximates to
10
%
×
=
cycle
duty
PWM
fanspeed
STEP 4—PWMMAX FOR PWM (FAN) OUTPUTS
PWMMAX is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For maximum
system acoustic benefit, PWMMAX should be as low as possible
but should be capable of maintaining the processor temperature
limit at an acceptable level. If the THERM temperature limit is
exceeded, the fans are still boosted to 100% for fail-safe cooling.
There is one PWMMAX limit (Register 0x2C) for all fan channels.
TEMPERATURE
TMIN
100%
PWMMIN
0%
PW
M
DU
TY
CYC
L
E PWM
MAX
055
69-
045
Figure 57. PWMMAX Determines Maximum PWM Duty Cycle
Below the THERM Temperature Limit
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