參數(shù)資料
型號(hào)： ADT7462ACPZ-500RL7
廠商： ON SEMICONDUCTOR
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, LFCSP-32
文件頁數(shù)： 77/88頁
文件大?。?/td> 836K
代理商： ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 79 of 88 | www.onsemi.com
Table 73. Register 0x36—GPIO Mask Register1
Bit
Name
R/W
Description
0
GPIO1
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1
GPIO2
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
2
GPIO3
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
3
GPIO4
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
4
GPIO5
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
5
GPIO6
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
6
GPIO7
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
7
GPIO8
R/W
A 1 masks ALERTs for the corresponding interrupt status bit.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 74. Register 0x37—EDO 1 Mask Register1
Bit
Name
R/W
Description
0
GPIO1
R/W
A 1 masks GPIO1 from causing an EDO1 assertion.
1
GPIO2
R/W
A 1 masks GPIO2 from causing an EDO1 assertion.
2
GPIO3
R/W
A 1 masks GPIO3 from causing an EDO1 assertion.
3
GPIO4
R/W
A 1 masks GPIO4 from causing an EDO1 assertion.
4
Reserved
R/W
Unused.
5
Fan
R/W
A 1 masks a fan-fail condition from causing an EDO1 assertion.
6
Temp
R/W
A 1 masks a THERM condition from causing an EDO1 assertion.
7
Volt
R/W
A 1 masks a voltage exceed limit condition from causing an EDO1 assertion.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 75. Register 0x38—EDO 2 Mask Register1
Bit
Name
R/W
Description
0
GPIO1
R/W
A 1 masks GPIO1 from causing an EDO2 assertion.
1
GPIO2
R/W
A 1 masks GPIO2 from causing an EDO2 assertion.
2
GPIO3
R/W
A 1 masks GPIO3 from causing an EDO2 assertion.
3
GPIO4
R/W
A 1 masks GPIO4 from causing an EDO2 assertion.
4
Reserved
R/W
Unused.
5
Fan
R/W
A 1 masks a fan-fail condition from causing an EDO2 assertion.
6
Temp
R/W
A 1 masks a THERM condition from causing an EDO2 assertion.
7
Volt
R/W
A 1 masks a voltage exceed limit condition from causing an EDO2 assertion.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 76. Register 0x3D—Device ID Register1
Bit
Name
R/W
Description
[7:0]
Device ID
R
This register contains the device ID (0x62) for the ADT7462.
1 POR = 0x62, SW Reset = N.
Table 77. Register 0x3E—Company ID Register1
Bit
Name
R/W
Description
[7:0]
Company ID
R
This register contains the company ID (0x41) for the ADT7462.
1 POR = 0x41, SW Reset = N.
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