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參數(shù)資料
| 型號： | ADT7462ACPZ-500RL7 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT |
| 封裝： | 5 X 5 MM, LFCSP-32 |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 836K |
| 代理商： | ADT7462ACPZ-500RL7 |
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ADT7462
Rev. 2 | Page 57 of 88 | www.onsemi.com
GENERAL-PURPOSE I/O PINS
The ADT7462 has eight open-drain GPIO pins. GPIO1 to
GPIO4 can be configured to enable event driven outputs
(EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO
functionality is enabled. Two other GPIOs (GPIO7 and GPIO8)
are standard GPIO pins that are dedicated to general-purpose
logic input/output.
Each GPIO pin has five data bits associated with it: three bits in
a GPIO configuration register (0x09 and 0x0A), one in the
GPIO status register (0xBF), and one in the GPIO mask register
(0x36).
Setting a direction bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin an output.
Clearing the direction bit to 0 makes the corresponding GPIO
pin an input.
Setting a polarity bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes the corresponding GPIO
pin active low.
When a GPIO pin is configured as an input, the corresponding
bit in the GPIO status register is read-only, and it is set when
the input is asserted (“asserted” can be high or low, depending
on the setting of the polarity bit).
When a GPIO pin is configured as an output, the corresponding
bit in the GPIO status register becomes read/write. Setting this
bit then asserts the GPIO output. (Again, “asserted” can be high
or low, depending on the setting of the polarity bit.) The effect
of a GPIO status register bit on the ALERT output can be
masked by setting the corresponding bit in one of the GPIO
mask registers.
When the pin is configured as an output, the corresponding status
bit is automatically masked to prevent the data written to the status
bit from causing an interrupt. When configured as inputs, the
GPIO pins can be connected to external interrupt sources such
as temperature sensors with digital output.
EDO CIRCUITRY
The ADT7462 has the added functionality that the assertion
of one of the four GPIOs (GPIO1 to GPIO4) can be used to
latch one of the two EDOs high or low. The ADT7462 has two
EDO event mask registers (0x37 and 0x38): one mask for each
EDO. See Table 33 for an explanation of event mask register
functionality.
The polarity of the EDOs is set in the GPIO configuration
registers (0x09 and 0x0A).
Setting a polarity bit to 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes it active low.
GPIO1
GPIO2
GPIO3
GPIO4
LATCH
EVENT
MASK
EDO (GPIO5)
EDO (GPIO6)
055
69-
074
Figure 85. EDO Circuit
Bits [7:5] of each event mask register (0x37 and 0x38) allow the
EDO output to be driven high or low (depending on the polarity
bit of the configuration register) and latched (depending on the
EDO latch bit of the configuration register), if the ADT7462 detects
an overtemperature, an overvoltage/undervoltage, or a fan failure
condition.
Table 33. EDO Control (Mask) Register 0x37 and Register 0x38
Bit 7: Overvoltage/
Undervoltage
Bit 6: THERM
Bit 5: Fan Fail
Bit 3
Bit 2
Bit 1
Bit 0
Behavior: What Drives and Latches Output X
(G = GPIO)
0 = Drive
Output X
0 = Drive
Output X
0 = Drive
Output X
0
G4 or G3 or G2 or G1
1 = Ignore Event
0
1
G4 or G3 or G2
0
1
0
G4 or G3 or G1
0
1
G4 or G3
0
1
0
G4 or G2 or G1
0
1
0
1
G4 or G2
0
1
0
G4 or G1
0
1
G4
1
0
G3 or G2 or G1
1
0
1
G3 or G2
1
0
1
0
G3 or G1
1
0
1
G3
1
0
G2 or G1
1
0
1
G2
1
0
G1
1
GPIO events ignored by Output X
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