參數(shù)資料
型號： ADT7462ACPZ-500RL7
廠商： ON SEMICONDUCTOR
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, LFCSP-32
文件頁數(shù)： 48/88頁
文件大?。?/td> 836K
代理商： ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 52 of 88 | www.onsemi.com
Effect of Ramp Rate on Enhanced Acoustic Mode
The PWM signal driving the fan has a period, t, given by the
PWM drive frequency, f, because t = 1/f. For a given PWM
period, t, the PWM period is subdivided into 255 equal time
slots. One time slot corresponds to the smallest possible incre-
ment in the PWM duty cycle. A PWM signal of 33% duty cycle
is, therefore, high for 1/3 × 255 time slots and low for 2/3 × 255
time slots. Therefore, a 33% PWM duty cycle corresponds to a
signal that is high for 85 time slots and low for 170 time slots.
170
TIME SLOTS
85
TIME SLOTS
PWM OUTPUT
(ONE PERIOD)
=255 TIME SLOTS
PWM_OUT
33% DUTY
CYCLE
05
569
-0
65
Figure 76. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in the enhanced acoustics mode are selectable
from 1 to 8. The ramp rates are discrete time slots. For example,
if the ramp rate is 8, then eight time slots are added to the PWM
high duty cycle each time the PWM duty cycle needs to be
increased. If the PWM duty cycle value needs to be decreased,
it is decreased by eight time slots. Figure 77 shows how the
enhanced acoustics mode algorithm operates.
READ
TEMPERATURE
CALCULATE
NEW PWM
DUTY CYCLE
IS NEW PWM
VALUE >
PREVIOUS
VALUE?
INCREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
YES
NO
DECREMENT
PREVIOUS
PWM VALUE
BY RAMP RATE
055
69-
066
Figure 77. Enhanced Acoustics Mode Algorithm
The enhanced acoustics mode algorithm calculates a new PWM
duty cycle based on the temperature measured. If the new
PWM duty cycle value is greater than the previous PWM value,
the previous PWM duty cycle value is incremented by either 1,
2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of
the enhanced acoustics registers. If the new PWM duty cycle
value is less than the previous PWM value, the previous PWM
duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots.
Each time the PWM duty cycle is incremented or decremented,
its value is stored as the previous PWM duty cycle for the next
comparison.
A ramp rate of 1 corresponds to one time slot, which is 1/255 of
the PWM period. In enhanced acoustics mode, incrementing or
decrementing by 1 changes the PWM output by 1/255 × 100%.
STEP 11—RAMP RATE FOR ACOUSTIC
ENHANCEMENT
The optimal ramp rate for acoustic enhancement can be found
through system characterization after the thermal optimization
has been finished. The effect of each ramp rate should be logged, if
possible, to determine the best setting for a given solution.
Enhanced Acoustics Register 1 (0x1A)
Bits [4:2] RR1 select the ramp rate for PWM1.
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
Bits [7:5] RR2 select the ramp rate for PWM2.
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
Enhanced Acoustics Register 2 (0x1B)
Bits [4:2] RR3 select the ramp rate for PWM3.
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
Bits [7:5] RR4 select the ramp rate for PWM4.
000 = 1 time slot = 35 seconds
001 = 2 time slots = 17.6 seconds
010 = 3 time slots = 11.8 seconds
011 = 5 time slots = 7 seconds
100 = 8 time slots = 4.4 seconds
101 = 12 time slots = 3 seconds
110 = 24 time slots = 1.6 seconds
111 = 48 time slots = 0.8 seconds
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