參數(shù)資料
型號(hào)： ADT7462ACPZ-500RL7
廠商： ON SEMICONDUCTOR
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, LFCSP-32
文件頁(yè)數(shù)： 75/88頁(yè)
文件大小： 836K
代理商： ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 77 of 88 | www.onsemi.com
Table 65. Minimum PWMx Duty Cycle1
Register Address
R/W
Description
POR Default
0x28
R/W
Minimum PWM1 duty cycle
0x80
0x29
R/W
Minimum PWM2 duty cycle
0x80
0x2A
R/W
Minimum PWM3 duty cycle
0x80
0x2B
R/W
Minimum PWM4 duty cycle
0x80
1 Lock = Y, SW Reset = Y.
Table 66. Register 0x2C—Maximum PWM Duty Cycle1
Bit
Name
R/W
Description
[7:0]
Maximum PWM Duty Cycle
R/W
This register sets the maximum % duty cycle output in automatic fan speed
control mode for all four PWM outputs.
1 POR = 0xC0, Lock = Y, SW Reset = Y.
Table 67. Register 0x30—Thermal Mask Register 11
Bit
Name
R/W
Description
0
Reserved
R/W
Reserved for future use.
1
Local Temp
R/W
1 masks ALERTs for an out-of-limit condition on the local temperature channel.
2
Remote 1 Temp
R/W
1 masks ALERTs for an out-of-limit condition on the Remote 1 temperature channel.
3
Remote 2 Temp
R/W
1 masks ALERTs for an out-of-limit condition on the Remote 2 temperature channel.
4
Remote 3 Temp
R/W
1 masks ALERTs for an out-of-limit condition on the Remote 3 temperature channel.
5
Diode 1 Error
R/W
1 masks ALERTs for an open or short condition on the Remote 1 channel.
6
Diode 2 Error
R/W
1 masks ALERTs for an open or short condition on the Remote 2 channel.
7
Diode 3 Error
R/W
1 masks ALERTs for an open or short condition on the Remote 3 channel.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 68. Register 0x31—Thermal Mask Register 21
Bit
Name
R/W
Description
0
THERM1 %
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
1
THERM1 Assert
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
2
THERM1 State
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
3
THERM2 %
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
4
THERM2 Assert
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
5
THERM2 State
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
6
VRD1_Assert
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
7
VRD2_Assert
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
1 POR = 0xC0, Lock = N, SW Reset = Y.
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