參數(shù)資料
型號(hào): ADT7462ACPZ-500RL7
廠商: ON SEMICONDUCTOR
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝: 5 X 5 MM, LFCSP-32
文件頁(yè)數(shù): 76/88頁(yè)
文件大?。?/td> 836K
代理商: ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 78 of 88 | www.onsemi.com
Table 69. Register 0x32—Voltage Mask Register 11
Bit
Name
R/W
Description
0
+12V1
R/W
1 masks ALERTs for the corresponding interrupt status bit.
1
+12V2
R/W
1 masks ALERTs for the corresponding interrupt status bit.
2
+12V3
R/W
1 masks ALERTs for the corresponding interrupt status bit.
3
+3.3V
R/W
1 masks ALERTs for the corresponding interrupt status bit.
4
Pin 15 Voltage
R/W
1 masks ALERTs for the corresponding interrupt status bit.
5
Pin 19 Voltage
R/W
1 masks ALERTs for the corresponding interrupt status bit.
6
+5V
R/W
1 masks ALERTs for the corresponding interrupt status bit.
7
Pin 23 Voltage
R/W
1 masks ALERTs for the corresponding interrupt status bit.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 70. Register 0x33—Voltage Mask Register 21
Bit
Name
R/W
Description
[2:0]
Reserved
R/W
Reserved for future use.
3
Pin 24 Voltage
R/W
1 masks ALERTs for the corresponding interrupt status bit.
4
Pin 25 Voltage
R/W
1 masks ALERTs for the corresponding interrupt status bit.
5
Pin 26 Voltage
R/W
1 masks ALERTs for the corresponding interrupt status bit.
6
+1.5V2 (3GIO)
R/W
1 masks ALERTs for the corresponding interrupt status bit.
7
+1.5V1 (ICH)
R/W
1 masks ALERTs for the corresponding interrupt status bit.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 71. Register 0x34—Fan Mask Register1
Bit
Name
R/W
Description
0
Fan 1 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
1
Fan 2 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
2
Fan 3 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
3
Fan 4 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
4
Fan 5 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
5
Fan 6 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
6
Fan 7 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
7
Fan 8 Fault
R/W
1 masks ALERTs for the corresponding interrupt status bit.
1 POR = 0x00, Lock = N, SW Reset = Y.
Table 72. Register 0x35—Digital Mask Register1
Bit
Name
R/W
Description
[2:0]
Reserved
R
Reserved for future use.
3
FAN2MAX
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
4
SCSI1
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
5
SCSI2
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
6
VID Comparison
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
7
Chassis Intrusion
R/W
1 masks ALERTs for the corresponding interrupt status bit. Default = 0.
1 POR = 0x38, Lock = N, SW Reset = Y.
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