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參數(shù)資料
| 型號： | ADT7462ACPZ-500RL7 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT |
| 封裝： | 5 X 5 MM, LFCSP-32 |
| 文件頁數(shù)： | 54/88頁 |
| 文件大小： | 836K |
| 代理商： | ADT7462ACPZ-500RL7 |
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ADT7462
Rev. 2 | Page 58 of 88 | www.onsemi.com
Table 33 shows that any of the four designated GPIO pins can
be used to set or reset either one of the two EDO outputs.
Using this functionality, it is possible to have the ADT7462
drive LEDs or signals based on rules. For example, if a GPIO1
(power fail), a GPIO2 (overcurrent), or an overtemperature
condition occurs, EDO1 (power supply fault LED) can be
latched. This does not require software handling and makes the
part more autonomous.
OTHER DIGITAL INPUTS
The ADT7462 contains other specific digital inputs that can be
found on PC motherboards. These inputs can be monitored and
configured for actions to occur on their assertion.
VR_HOT Inputs
Pin 25 and Pin 26 can be configured as VR_HOT inputs. These
are specific digital signals from the CPU voltage regulator that
indicate an overtemperature. On assertion of these inputs, the
relevant status bits are set in Thermal Status Register 2 (Host
Register 0xB9 or BMC Register 0xC1). Assertion of these inputs
can also be used to boost the fans to full speed, thus providing
emergency cooling in the event of VR overtemperature. This is set
using Bit 3 (VRD1) and Bit 4 (VRD2) of Configuration Register
2 (0x02). There is also an associated mask bit in Register 0x31
to mask the assertion of these inputs from the ALERT output.
SCSI_TERM Inputs
Pin 16 and Pin 20 can be configured as SCSI_TERM inputs.
An assertion on the SCSI_TERM is recorded in Bit 4 and Bit 5
of Host Digital Status Register (0xBE) or BMC Digital Status
Register (0xC6). There is also an associated mask bit in Register
0x35 to mask the assertion of these inputs from the ALERT
output.
RESET I/O
The ADT7462 includes an active low reset pin (Pin 14). The
RESET pin can be both a reset input and output. RESET
monitors the VCC input to the ADT7462. At power-up, RESET
is asserted (pulled low) until 180 ms after the power supply has
risen above the supply threshold. A power-on reset initializes all
registers to the default values.
1V
180ms
05
569-
075
VCC
RESET
Figure 86. Operation of RESET Output on Power-Up
The RESET pin can also function as a reset input. Pulling this
pin low externally resets the ADT7462. The user should wait at
least 180 ms after power-up before doing a hardware reset. The
reset pulse width should be greater than 0.8 ms to ensure that a
reset is registered.
A hardware reset differs from a power-on reset in that not all of
the registers are reinitialized to the default values. For example,
limit registers are not all restored to the default values. This can
be useful if the user needs to reset the part but does not want to
completely reprogram the device. The Register Map section shows
which registers are reset. Locked registers are not restored to
default values by a hardware reset.
Note that if two ADT7462 devices are used in one system, the
RESET pins should not be connected together between devices.
Doing so causes one device to reset the other on a power-on reset.
Software Reset
The ADT7462 can be reset in software by setting Bit 7 of
Configuration Register 0 (0x00). The code 0x6D must be written to
Register 0x7B before setting the software reset bit. This register is
cleared to the power-on default after the software reset.
Note that not all registers are restored to their default values on
a reset. The same registers are reset by a hardware and software
reset. The Register Map section provides a complete reference
of registers that are reset.
CHASSIS INTRUSION INPUT
The chassis intrusion (CI) input is an active high input intended
for detection and signaling of unauthorized tampering with the
system. When this input goes high, the event is latched in Bit 7
of Host Digital Status Register (0xBE), and an interrupt is gener-
ated. The bit remains set until cleared by writing a 1 to CI reset
(CI_R), Bit 5 of Configuration Register 3 (0x03). The CI reset
bit is cleared by writing a 0 to it.
The CI circuit is powered from the VBATT voltage channel. Pin 26
must be configured to monitor VBATT and a battery must be
connected to monitor CI events. CI monitoring is disabled if
the measured VBATT value (0x93) is less than the lower voltage
limit (0x75) of Pin 26.
The CI input detects chassis intrusion events even when the
ADT7462 is powered off (provided battery voltage is applied to
VBATT) but does not immediately generate an interrupt. When a
chassis intrusion event is detected and latched, an interrupt is
generated when the system is powered on.
The actual detection of chassis intrusion is performed by an
external circuit that detects, for example, when the cover has
been removed. A wide variety of techniques can be used for
chassis detection. For example,
A microswitch that opens or closes when the cover is removed
A reed switch operated by a magnet affixed to the cover
A hall-effect switch operated by a magnet affixed to the cover
A phototransistor that detects light when the cover is
removed
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