參數(shù)資料
型號： ADT7462ACPZ-500RL7
廠商： ON SEMICONDUCTOR
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝： 5 X 5 MM, LFCSP-32
文件頁數(shù)： 71/88頁
文件大?。?/td> 836K
代理商： ADT7462ACPZ-500RL7
ADT7462
Rev. 2 | Page 73 of 88 | www.onsemi.com
Table 56. Register 0x1A—Enhanced Acoustics Register 11
Bit
Name
R/W
Description
0
En1
R/W
Setting this bit to 1 enables the enhanced acoustics mode for PWM1; 0 disables it. Default = 0.
1
En2
R/W
Setting this bit to 1 enables the enhanced acoustics mode for PWM2; 0 disables it. Default = 0.
[4:2]
Ramp Rate 1
R/W
These bits set the ramp rate for the enhanced acoustics mode for PWM1. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
[7:5]
Ramp Rate 2
R/W
These bits set the ramp rate for the enhanced acoustics mode for PWM2. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
1 POR = 0x00, Lock = Y, SW Reset = Y.
Table 57. Register 0x1B—Enhanced Acoustics Register 21
Bit
Name
R/W
Description
0
En3
R/W
Setting this bit to 1 enables the enhanced acoustics mode for PWM3; 0 disables it. Default = 0.
1
En4
R/W
Setting this bit to 1 enables the enhanced acoustics mode for PWM4; 0 disables it. Default = 0.
[4:2]
Ramp Rate 3
R/W
These bits set the ramp rate for the enhanced acoustics mode for PWM3. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
[7:5]
Ramp Rate 4
R/W
These bits set the ramp rate for the enhanced acoustics mode for PWM4. Default = 000.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
1 POR = 0x00, Lock = Y, SW Reset = Y.
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