參數(shù)資料
型號: ADSP-TS101SKB2250X
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 125 MHz, OTHER DSP, PBGA484
封裝: 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件頁數(shù): 8/42頁
文件大?。?/td> 774K
代理商: ADSP-TS101SKB2250X
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
16
REV. PrE
PRELIMINARY TECHNICAL DATA
LDQM
O/T (pu)
Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. LDQM is valid on SDRAM transactions when
CAS is asserted, and inactive
on read transactions. On write transactions, LDQM is active when accessing an odd
address word on a 64-bit memory bus to disable the write of the low word.
HDQM
O/T (pu)
High Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. HDQM is valid on SDRAM transactions when
CAS is asserted, and inactive
on read transactions. On write transactions, HDQM is active when accessing an even
address in word accesses or when memory is configured for a 32-bit bus to disable the
write of the high word.
SDA10
O/T (pu)
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation
while the DSP executes non-SDRAM transactions.
SDCKE
I/O/T
(pu/pd)
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or
suspend modes. A slave DSP in a multiprocessor system does not have the pullup or
pulldown. A master DSP (or ID=0 in a single processor system) has a 100 k
pullup
before granting the bus to the host, except when the SDRAM is put in self refresh
mode. In self refresh mode, the master has a 100 k
pulldown before granting the bus
to the host.
SDWE1
I/O/T (pu)
SDRAM Write Enable. When sampled low while
CAS is active, SDWE indicates an
SDRAM write access. When sampled high while
CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses,
SDWE defines the type of operation
to execute according to SDRAM specification.
1 The internal 100 k
internal pullup may not be sufficient depending on system noise and/or leakage. A stronger pullup may be necessary.
2 The internal 100 k
internal pulldown may not be sufficient depending on system noise and/or leakage. A stronger pulldown may be necessary.
Table 7. Pin Definitions—JTAG Port
Signal
Type
Description
EMU
O (o/d)
Emulation. Connected to the DSP’s JTAG emulator target board connector only.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
TDI
1
I (pu)
Test Data Input (JTAG). A serial data input of the scan path.
TDO
O/T
Test Data Output (JTAG). A serial data output of the scan path.
TMS
I (pu)
Test Mode Select (JTAG). Used to control the test state machine.
TRST1
I/A (pu)
Test Reset (JTAG). Resets the test state machine.
TRST must be asserted or pulsed
low after power up for proper device operation. For more information, see Reset and
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
1 The internal 100 k
internal pullup may not be sufficient depending on system noise and/or leakage. A stronger pullup may be necessary.
Table 6. Pin Definitions—SDRAM Controller (continued)
Signal
Type
Description
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
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