
This information applies to a product under development. Its characteristics and specifications are subject to change with-
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ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
CPA
I/O (o/d)
Core Priority Access. Asserted while the DSP’s core accesses external memory. This
pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and
gain control of the external bus for core-initiated transactions.
CPA is an open drain
output, connected to all DSPs in the system. The
CPA pin has an internal 500
pullup resistor, which is only enabled on the DSP with ID=0. If not required in the
system, leave
CPA unconnected (external pullups will be required for ID1–ID7).
DPA
I/O (o/d)
DMA Priority Access. Asserted while a high-priority DSP DMA channel accesses
external memory. This pin enables a high-priority DMA channel on a slave DSP to
interrupt transfers of a normal-priority DMA channel on a master DSP and gain
control of the external bus for DMA-initiated transactions.
DPA is an open drain
output, connected to all DSPs in the system. The
DPA pin has an internal 500
pullup resistor, which is only enabled on the DSP with ID=0. If not required in the
system, leave
DPA unconnected (external pullups will be required for ID1–ID7).
DMAR3–0
I/A
DMA Request Pins. Enable external I/O devices to request DMA services from the
DSP. In response to
DMARx, the DSP performs DMA transfers according to the
DMA channel’s initialization. The DSP ignores DMA requests from uninitialized
channels.
O/T (pu)
Flyby Mode. When a DSP DMA channel is initiated in
FLYBY mode, it generates
flyby transactions on the external bus. During flyby transactions, the DSP asserts
FLYBY, which signals the source or destination I/O device to latch the next data or
strobe the current data, respectively, and to prepare for the next data on the next cycle.
O/T (pu)
I/O Device Output Enable. Enables the output buffers of an external I/O device for
fly-by transactions between the device and external memory. Active on fly-by
transactions.
1 The address and data buses may float for several cycles during bus mastership transitions between a TigerSHARC and a host. Floating in this case means
that these inputs are not driven by any source and that DC-biased terminations are not present. It is not necessary to add pullups as there are no reliability
issues and the worst-case power consumption for these floating inputs is negligible. Unconnected address pins may require pullups or pulldowns to avoid
erroneous slave accesses, depending on the system. Unconnected data pins may be left floating.
2 The internal 100 k
internal pullup may not be sufficient depending on system noise and/or leakage. A stronger pullup may be necessary.
3 The internal 100 k
internal pulldown may not be sufficient depending on system noise and/or leakage. A stronger pulldown may be necessary.
Table 6. Pin Definitions—SDRAM Controller
Signal
Type
Description
MSSD1
I/O/T (pu)
Memory Select SDRAM.
MSSD is asserted whenever the DSP accesses SDRAM
memory space.
MSSD is a decoded memory address pin that is asserted whenever the
DSP issues an SDRAM command cycle (access to ADDR31:26 = 0b000001). In a
multiprocessor system, the master DSP drives
MSSD.
I/O/T (pu)
Row Address Select. When sampled low,
RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
I/O/T (pu)
Column Address Select. When sampled low,
CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
Table 5. Pin Definitions—External Port (continued)
Signal
Type
Description
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State