參數(shù)資料
型號： ADSP-TS101SKB2250X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 125 MHz, OTHER DSP, PBGA484
封裝： 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件頁數(shù)： 15/42頁
文件大?。?/td> 774K
代理商： ADSP-TS101SKB2250X
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
22
REV. PrE
PRELIMINARY TECHNICAL DATA
TIMING SPECIFICATIONS
With the exception of Link port,
DMAR3–0, and IRQ3–0 pins,
all AC timing for the ADSP-TS101S is relative to a reference
clock edge. Because input setup/hold, output valid/hold, and
output enable/disable times are relative to a clock edge, the timing
data for the ADSP-TS101S has few calculated (formula-based)
values.For information on AC timing, see General AC Timing
on page 22. For information on Link port transfer timing, see
General AC Timing
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 10 on page 24. All delays (in nanoseconds)
are measured between the point that the first signal reaches 1.5 V
and the point that the second signal reaches 1.5 V.
The general AC timing data appears in Table 16 and Table 17.
The AC asynchronous timing data for the
IRQ3–0 and
DMAR3–0 pins appears in Table 15.
Table 15. AC Asynchronous Signal Specifications (all values in this table are in nanoseconds)
Name
Description
Pulsewidth Low (min)
Pulsewidth High (min)
IRQ3–01
Interrupt Request
tCCLK + TBD ns
DMAR3–01
DMA Request
tCCLK + 3 ns
1 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
Table 16. Reference Clocks
Signal
Type
Description
Speed
Grade
(MHz)
Clock
Cycle
Min (ns)
Clock
Cycle
Max (ns)
Clock
High
Min (ns)
Clock
Low
Min (ns)
Skew to
LCLK
Max (ps)
CCLK
1
–
Core Clock
250
4.0
12.5
–––
LCLK_P
2,3
I
Local Clock
250
CR
×4.0
CR
×12.5
{40% to 60%
Duty Cycle}
–
SCLK_P
ISystem Clock,
SCLKFREQ = 1
All
Greater of 10
CCLK
×2
20
{40% to 60%
Duty Cycle}
50
System Clock,
SCLKFREQ = 0
All
Greater of 20
or CCLK
×2
50
TCK
I
Test Clock (JTAG)
All
Greater of 30
or CCLK
×4
–
12
–
1 CCLK is the internal DSP clock or instruction cycle time. The period of this clock is equal to the Local Clock (LCLK_P) period divided by the Local
Clock Ratio (LCLKRAT2–0). For information on available internal DSP clock rates, see the Ordering Guide on page 42.
2 The Core clock Ratio (CR) is 2, 2.5, 3, 3.5, 4, 5, or 6 as set by the LCLKRAT2–0 pins. For more information, see Table 4 on page 13.
4 For more information, see Table 3 on page 12.
Table 17. AC Signal Specifications (all values in this table are in nanoseconds)
Name
Description
Input
Setup
(min)
Input
H
o
ld
(min)
O
u
tput
V
a
lid
(m
ax)
O
u
tput
H
o
ld
(min)
O
u
tput
Enab
le
(m
ax)
1
O
u
tput
D
isab
le
(m
ax)
Ref
e
rence
Clock
ADDR31–0
External Address Bus
1.5
0.5
4
1
1.5
4
SCLK
DATA63–0
External Data Bus
1.5
0.5
411.5
4SCLK
MSH
Memory Select HOST Line
——
411.5
4SCLK
MSSD
Memory Select SDRAM Line
1.5
0.5
411.5
4SCLK
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