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| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 34/42頁 |
| 文件大小： | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
4
REV. PrE
PRELIMINARY TECHNICAL DATA
The compute blocks are referred to as CBX and CBY in assembly
syntax, and each block contains three computational units—an
ALU, a multiplier, a 64-bit shifter—and a 32-word register file.
Register File—Each Compute Block has a multiported
32-word, fully orthogonal register file used for transfer-
ring data between the computation units and data buses
and for storing intermediate results. Instructions can
access the registers in the register file individually (word-
aligned), or in sets of two (dual-aligned) or four (quad-
aligned).
ALU—The ALU performs a standard set of arithmetic
operations in both fixed- and floating-point formats. It
also performs logic operations.
Multiplier—The multiplier performs both fixed- and
floating-point multiplication and fixed-point multiply and
accumulate.
Shifter—The 64-bit shifter performs logical and arith-
metic shifts, bit and bitstream manipulation, and field
deposit and extraction operations.
Accelerator—128-bit unit for Trellis Decoding (for
example, Viterbi and Turbo decoders) and complex cor-
relations for communication applications
Using these features, the compute blocks can:
Provide 8 MACs per cycle peak and 7.1 MACs per cycle
sustained 16-bit performance and provide 2 MACs per
cycle peak and 1.8 MACs per cycle sustained 32-bit per-
formance (based on FIR)
Execute six single-precision floating-point or execute
twenty-four 16-bit fixed-point operations per cycle,
providing 1500 MFLOPS or 6.0 GOPS performance
Performs two complex 16-bit MACs per cycle
Executes eight Trellis butterflies in one cycle
Data Alignment Buffer (DAB)
The DAB is a two quad-word FIFO that enables loading of quad-
word data from nonaligned addresses. Normally, load instruc-
tions must be aligned to their data size so that quad words are
loaded from a quad-aligned address. Using the DAB significantly
improves the efficiency of some applications, such as FIR filters.
Dual Integer ALUs (IALUs)
The ADSP-TS101S has two IALUs that provide powerful
address generation capabilities and perform many general-
purpose integer operations. The IALUs have the following
features:
Provides memory addresses for data and update pointers
Supports circular buffering and bit-reverse addressing
Performs general-purpose integer operations, increasing
programming flexibility
Includes a 31-word register file for each IALU
As address generators, the IALUs perform immediate or indirect
(pre- and post-modify) addressing. They perform modulus and
bit-reverse operations with no constraints placed on memory
addresses for the modulus data buffer placement. Each IALU can
specify either a single-, dual-, or quad-word access from memory.
The IALUs have hardware support for circular buffers, bit
reverse, and zero-overhead looping. Circular buffers facilitate
efficient programming of delay lines and other data structures
required in digital signal processing, and they are commonly used
in digital filters and Fourier transforms. Each IALU provides
registers for four circular buffers, so applications can set up a total
of eight circular buffers. The IALUs handle address pointer wrap-
around automatically, reducing overhead, increasing
performance, and simplifying implementation. Circular buffers
can start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle.
Hardware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
Program Sequencer
The ADSP-TS101S’s program sequencer supports the
following:
A fully interruptible programming model with flexible
programming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles
An eight-cycle instruction pipeline—three-cycle fetch
pipe and five-cycle execution pipe—computation results
available two cycles after operands are available
Supply of instruction fetch memory addresses; the
sequencer’s Instruction Alignment Buffer (IAB) caches
up to five fetched instruction lines waiting to execute; the
program sequencer extracts an instruction line from the
IAB and distributes it to the appropriate core component
for execution.
Management of program structures and program flow deter-
mined according to JUMP, CALL, RTI, RTS
instructions, loop structures, conditions, interrupts, and
software exceptions
Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero-to-two overhead cycles, over-
coming the three- to-six stage branch penalty
Compact code without the requirement to align code in
memory; the IAB handles alignment
Interrupt Controller
The DSP supports nested and nonnested interrupts. Each
interrupt type has a register in the interrupt vector table. Also,
each has a bit in both the interrupt latch register and the interrupt
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| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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