參數(shù)資料
型號(hào)： ADSP-TS101SKB2250X
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 125 MHz, OTHER DSP, PBGA484
封裝： 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件頁(yè)數(shù)： 25/42頁(yè)
文件大?。?/td> 774K
代理商： ADSP-TS101SKB2250X
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
31
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L and the
load current, IL. This decay time can be approximated by the
following equation:
tDECAY = (CLV)/IL
The output disable time tDIS is the difference between
tMEASURED_DIS and tDECAY as shown in Figure 19. The time
tMEASURED_DIS is the interval from when the reference signal
switches to when the output voltage decays
V from the
measured output high or output low voltage. tDECAY is calculated
with test loads CL and IL, and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The time for the voltage on the bus to ramp by
V is
dependent on the capacitive load, CL, and the drive current, ID.
This ramp time can be approximated by the following equation:
tRAMP = (CLV)/ID
The output enable time tENA is the difference between
tMEASURED_ENA and tRAMP as shown in Figure 19. The time
tMEASURED_ENA is the interval from when the reference signal
switches to when the output voltage ramps
V from the measured
three-stated output level. tRAMP is calculated with test load CL,
drive current ID, and with V equal to 0.5 V.
Capacitive Loading
Output valid and holds are based on standard capacitive loads:
TBD on all pins (see Figure 20). The delay and hold specifica-
tions given should be derated by a factor of TBD ns/TBD pF for
loads other than the nominal value of TBD pF. Figure 21 and
Figure 22 show how output rise time varies with capacitance.
Figure 23 graphically shows how output valid and holds vary with
load capacitance. (Note that this graph or derating does not apply
to output disable delays; see Output Disable Time on page 31.)
The graphs of Figure 21, Figure 22, and Figure 23 may not be
linear outside the ranges shown.
Figure 20. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
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Figure 21. Typical Output Rise Time (10%–90%,
VDD_IO = Max) vs. Load Capacitance (at Default
Drive Strength and Default Impedance Control)
Figure 22. Typical Output Rise Time (10%–90%,
VDD_IO = Min) vs. Load Capacitance (at Default
Drive Strength and Default Impedance Control)
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