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參數(shù)資料
| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
19
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have a 100 k
pull-down for the default
value. If a strap pin is not connected to an external pull-up or
logic load, the DSP samples the default value during reset. If strap
pins are connected to logic inputs, a stronger external pulldown
may be required to ensure default value depending on leakage
and/or low level input current of the logic load. To set a mode
other than the default mode, connect the strap pin to a sufficiently
stronger external pull-up. Table 14 lists and describes each of the
DSP’s strap pins.
Table 13. Pin Definitions—Power, Ground, and Reference
Signal
Type
Description
VDD
PVDD pins for internal logic.
VDD_A
PVDD pins for analog circuits. Pay critical attention to bypassing this supply.
VDD_IO
PVDD pins for I/O buffers.
VREF
I
Reference voltage defines the trip point for all input buffers, except
RESET, IRQ3–0,
DMAR3–0, ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and TRST. The value is
1.5 V ± 100 mV (which is the TTL trip point). VREF can be connected to a power supply
or set by a voltage divider circuit. The voltage divider should have an HF decoupling
capacitor (1 nF HF SMD) connected to VSS. Tie the decoupling capacitor between VREF
VSS
G
Ground pins.
VSS_A
G
Ground pins for analog circuits.
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
Table 14. Pin Definitions—I/O Strap Pins
Signal
On Pin…
Description
EBOOT
BMS
EPROM boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP through the
external port or a link port
IRQEN
BM
Interrupt Enable.
0 = disable and set
IRQ3–0 interrupts to level-sensitive after reset (default)
1 = enable and set
IRQ3–0 interrupts to edge-sensitive immediately after reset
TM1
L2DIR
Test Mode 1.
0 = required setting during reset.
1 = reserved.
TM2
TMR0E
Test Mode 2.
0 = required setting during reset.
1 = reserved.
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| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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