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| 型號(hào)： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁(yè)數(shù)： | 12/42頁(yè) |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
2
REV. PrE
PRELIMINARY TECHNICAL DATA
TABLE OF CONTENTS
GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC DSP is an ultra-high perfor-
mance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting 32-bit floating-point and supporting 8-, 16-,
32-, and 64-bit fixed-point processing—to set a new standard of
performance for digital signal processors. The TigerSHARC
static superscalar architecture lets the DSP execute up to four
instructions each cycle, performing twenty-four 16-bit fixed-
point operations or six floating-point operations.
Three independent 128-bit wide internal data buses, each con-
necting to one of the three 2M bit memory banks, enable quad-
word data, instruction, and I/O accesses and provide 12G bytes
per second of internal memory bandwidth. Operating at
250 MHz, the ADSP-TS101S’s core has a 4.0 ns instruction
cycle time. Using its Single-Instruction, Multiple-Data (SIMD)
features, the ADSP-TS101S can perform 2 billion 40-bit MACs
show the DSP’s performance benchmarks.
The ADSP-TS101S is code-compatible with the other Tiger-
SHARC processors.
Table 1. General Purpose Algorithm Benchmarks
at 250 MHz
Benchmark
Speed
Clock
Cycles
32-bit Algorithm, 500 million MACs/s peak performance
1024 Point Complex FFT (Radix 2) 39.34 s
9,835
50-tap FIR on 1024 input
110 s
27,500
Single FIR MAC
2.2 ns
0.55
16-bit Algorithm, 2 billion MACs/s peak performance
256 Point Complex FFT (Radix 2) 4.4 s
1,100
50-tap FIR on 1024 input
28.8 s
7,200
Single FIR MAC
0.56 ns
0.14
Single Complex FIR MAC
2.28 ns
0.57
I/O DMA Transfer Rate
External port
800M bytes/s n/a
Link ports (each)
250M bytes/s n/a
Table 2. 3G Wireless Algorithm Benchmarks
Benchmark
Execution
(MIPS)
1
1 The Execution Speed is in Instruction Cycles Per Second.
Turbo Decode
384 kbps Data Channel
51 MIPS
Viterbi Decode
12.2 kbps AMR
2 Voice Channel
2 Adaptive Multi Rate (AMR)
0.86 MIPS
Complex Correlation
3.84 Mcps
3 with a Spreading Factor of 256
3 Megachips per second (Mcps)
0.27 MIPS
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| ADSP-TS201SABP-050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| ADSP-TS201SABP-060 | 功能描述:IC PROCESSOR 600MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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