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參數(shù)資料
| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 42/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
9
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
Reset and Booting
The ADSP-TS101S has three levels of reset:
Power-up reset—After power-up of the system, and strap
options are stable, the
RESET pin must be asserted (low)
for a minimum of 1 ms followed by a deasserted (high)
pulse of a minimum of 50 SCLK cycles and a maximum
of 100 SCLK cycles and asserted (low) for a minimum of
100 SCLK cycles.
TRST must also be asserted (low)
during power-up to ensure proper operation of the device.
See Figure 4.
Normal reset—For any resets following the power-up
reset sequence, the
RESET pin must be asserted for at
least 100 SCLK cycles.
Core reset—When setting the SQRST bit in SQCTL, the
core is reset, but not the external port or I/O.
After reset, the ADSP-TS101S has four boot options for
beginning operation:
Boot from EPROM. The DSP defaults to EPROM
booting when the
BMS pin strap option is set low. For
Boot by an external master (host or another ADSP-
TS101S). Any master on the cluster bus can boot the
ADSP-TS101S through writes to its internal memory or
through auto DMA.
Boot by link port. All four receive link DMA channels are
initialized after reset to transfer a 256-word block to
internal memory address 0 to 255, and to issue an
interrupt at the end of the block (similar to EP DMA).
The corresponding DMA interrupts are set to address
zero (0).
No boot—Start running from an external memory. Using
the ‘no boot’ option, the ADSP-TS101S must start
running from an external memory, caused by asserting
one of the
IRQ3–0 interrupt signals.
The ADSP-TS101S core always exits from reset in the idle state
and waits for an interrupt. Some of the interrupts in the interrupt
vector table are initialized and enabled after reset.
Low-Power Operation
The ADSP-TS101S can enter a low-power sleep mode, in which
its core does not execute instructions, reducing power consump-
tion to a minimum. The ADSP-TS101S exits sleep mode when
it senses a falling edge on any of its
IRQ3–0 interrupt inputs. The
interrupt, if enabled, causes the ADSP-TS101S to execute the
corresponding interrupt service routine. This feature is useful for
systems that require a low-power standby mode.
Clock Domains
The ADSP-TS101S has two clock inputs that drive its two major
clock domains:
SCLK (system clock). Provides clock input for the
external bus interface and defines the AC specification
reference for the external bus signals. The external bus
interface runs at 1
× the SCLK frequency. A DLL locks
internal SCLK to SCLK input. The maximum SCLK
frequency is one half the internal DSP clock (CCLK)
frequency. SCLK must be connected to the same clock
source as LCLK.
LCLK (local clock). Provides clock input to the internal
clock driver, CCLK, which is internal clock for the core,
internal buses, memory, and link ports. The instruction
execution rate is equal to CCLK. A PLL from LCLK
generates CCLK which is phase-locked. The LCLKRAT
pins define the clock multiplication of LCLK to CCLK
(see Table 4 on page 13). The link port clock is generated
from CCLK via a software programmable divisor.
RESET must be asserted until LCLK is stable and within
specification for at least 1 ms. This applies to power-up
as well as any dynamic modification of LCLK after power-
up. Dynamic modification may include LCLK going out
of specification as long as
RESET is asserted.
Connecting SCLK and LCLK to the same clock source is a
requirement for the device. Using an integer clock multiplication
value provides predictable cycle-by-cycle operation, a require-
ment of fault-tolerant systems and some multiprocessing
systems.
Power Supplies
The ADSP-TS101S has separate power supply connections for
internal logic (VDD), analog circuits (VDD_A), and I/O buffer
(VDD_IO) power supply. The internal (VDD) and analog (VDD_A)
supplies must meet the 1.2 V requirement. The I/O buffer
(VDD_IO) supply must meet the 3.3 V requirement.
Note that the analog (VDD_A) supply powers the clock generator
PLLs. To produce a stable clock, systems must provide a clean
power supply to power input VDD_A. Designs must pay critical
attention to bypassing the VDD_A supply.
The ideal power on sequence for the DSP is to provide power up
of all supplies simultaneously. If there is going to be some delay
between power up of the supplies, provide VDD (and VDD_A) first,
then VDD_IO.
Figure 4. Power-up Reset Waveform
RESET
NOTES:
tSTART_LO = 1ms MINIMUM AFTER POWER SUPPLIES ARE STABLE
tPULSE1_HI =50 SCLK MINIMUM TO 100 SCLK MAXIMUM
tPULSE2_LO =100 SCLK MINIMUM
tSTART_LO
tPULSE1_HI
tPULSE2_LO
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| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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