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參數(shù)資料
| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
12
REV. PrE
PRELIMINARY TECHNICAL DATA
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the EE-68:
Analog Devices JTAG Emulation Technical Reference on the Analog
Devices website—use site search on “EE-68”
(www.analog.com). This document is updated regularly to keep
pace with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-
TS101S’s architecture and functionality. For detailed informa-
tion on the ADSP-TS101S’s core architecture and instruction
set, see the TigerSHARC DSP Hardware Specification and the
TigerSHARC DSP Instruction Set Specification. For detailed infor-
mation on the development tools for this processor, see the
VisualDSP++ User’s Guide and Reference for the ADSP-TS101S
TigerSHARC DSP.
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS101S’s input pins are normally syn-
chronous—tied to a specific clock—a few are asynchronous. For
these asynchronous signals, an on-chip synchronization circuit
prevents metastability problems. The AC specification for asyn-
chronous signals is used only when having predictable cycle-by-
cycle behavior is required.
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these pins
to get to their internal pullup or pulldown state. Some output
pins (control signals) have a pullup or pulldown that maintain a
known value during transitions between different drivers.
Figure 9. JTAG Pod Connector Keep-Out Area
0.10"
0.15"
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Description
LCLK_N
I
LCLK_P
I
Local Clock Input. DSP clock input. The instruction cycle rate = n
× LCLK, where n
is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. For more information, see Clock
LCLKRAT2–0
1
I (pd)
LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n
× LCLK, where n is
user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These pins must
have a constant value while the DSP is powered.
SCLK_N
I
SCLK_P
I
System Clock Input. The DSP’s system input clock for cluster bus. This pin must be
connected to the same clock source as LCLK_P. For more information, see Clock
SCLKFREQ2
I (pu)
SCLK Frequency. Indicates the SCLK frequency range to the SCLK deskew PLL.
When SCLKFREQ = 0, SCLK =< 50 MHz. When SCLKFREQ = 1, SCLK =>
50 MHz (default). This pin must have a constant value while the DSP is powered.
RESET
I/A
Reset. Sets the DSP to a known state and causes program to be in idle state.
RESET
must be asserted a specified time according to the type of reset operation. For details,
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
1 The internal 100 k
internal pulldown may not be sufficient depending on system noise and/or leakage. A stronger pulldown may be necessary.
2 The internal 100 k
internal pullup may not be sufficient depending on system noise and/or leakage. A stronger pullup may be necessary.
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