參數(shù)資料
型號： ADSP-TS101SKB2250X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 125 MHz, OTHER DSP, PBGA484
封裝： 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件頁數(shù)： 23/42頁
文件大?。?/td> 774K
代理商： ADSP-TS101SKB2250X
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
The Functional Block Diagram on page 1 shows the ADSP-
TS101S’s architectural blocks. These blocks include:
Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and
associated Data Alignment Buffers (DABs)
Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing
A program sequencer with Instruction Alignment Buffer
(IAB), Branch Target Buffer (BTB), and interrupt
controller
Three 128-bit internal data buses, each connecting to one
of three 2M bit memory banks
On-chip SRAM (6M bit)
An external port that provides the interface to host pro-
cessors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
A DMA controller
Four link ports
Two 32-bit interval timers and timer expired pin
A 1149.1 IEEE compliant JTAG test access port for on-
chip emulation
Figure 1 on page 3 shows a typical single-processor system with
external SDRAM. Figure 3 on page 7 shows a typical multipro-
cessor system.
The TigerSHARC DSP uses a Static Superscalar
1 architecture.
This architecture is superscalar in that the ADSP-TS101S’s core
can execute simultaneously from one to four 32-bit instructions
encoded in a Very Large Instruction Word (VLIW) instruction
line using the DSP’s dual compute blocks. Because the DSP does
not perform instruction re-ordering at runtime—the program-
mer selects which operations will execute in parallel prior to
runtime, the order of instructions is static.
With few exceptions, an instruction line, whether it contains one,
two, three, or four 32-bit instructions, executes with a throughput
of one cycle in an eight-deep processor pipeline.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruction
line resources each instruction requires and on the source and
destination registers used in the instructions. The programmer
has direct control of three core components—the IALUs, the
compute blocks, and the program sequencer.
The ADSP-TS101S, in most cases, has a two-cycle execution
pipeline that is fully interlocked, so whenever a computation
result is unavailable for another operation dependent on it. The
DSP automatically inserts one or more stall cycles as needed.
Efficient programming with dependency-free instructions can
eliminate most computational and memory transfer data
dependencies.
In addition, the ADSP-TS101S supports SIMD operations two
ways—SIMD compute blocks and SIMD computations.The
programmer can direct both compute blocks to operate on the
same data (broadcast distribution) or on different data (merged
distribution). In addition, each compute block can execute four
16-bit or eight 8-bit SIMD computations in parallel.
Dual Compute Blocks
The ADSP-TS101S has compute blocks, that can execute com-
putations either independently or together as a Single-
Instruction, Multiple-Data (SIMD) engine. The DSP can issue
up to two compute instructions per compute block each cycle,
instructing the ALU, multiplier, or shifter to perform indepen-
dent, simultaneous operations.
1 Static Superscalar is a trademark of Analog Devices, Inc.
Figure 1. ADSP-TS101S single-processor system with
external SDRAM
CONTROLIMP2–0
DMAR3–0
DMA DEVICE
(OPTIONAL)
DATA
FLAG3–0
ID2–0
FLYBY
IOEN
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
IRQ3–0
LCLK_P
SCLK_P
LXCLKIN
LXDAT7–0
LXCLKOUT
LXDIR
LCLKRAT2–0
SCLKFREQ
TMR0E
BM
S/LCLK_N
VREF
MSSD
BUSLOCK
SDRAM
MEMORY
(OPTIONAL)
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
RESET
JTAG
ADSP-TS101
BMS
CLOCK
LINK
DEVICES
(4 MAX)
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY
(OPTIONAL)
OE
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
BR7–0
CPA
HBG
HBR
MS1–0
DATA63–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
D
A
T
A
C
O
N
T
R
O
L
A
D
R
E
S
BRST
REFERENCE
RD
WRH/WRL
MSH
DPA
BOFF
DS2–0
CS
相關(guān)PDF資料
PDF描述
ADT70GR-REEL7 ANALOG TEMP SENSOR-VOLTAGE, 2.49-2.51V, 1Cel, RECTANGULAR, SURFACE MOUNT
ADT7462ACPZ-500RL7 DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 4Cel, SQUARE, SURFACE MOUNT
ADTSM66SV KEYPAD SWITCH, SPST, MOMENTARY-TACTILE, 0.05A, 12VDC, 3.92 N, SURFACE MOUNT-STRAIGHT
ADTS644N/KV KEYPAD SWITCH, SPST, MOMENTARY-TACTILE, 0.05A, 12VDC, 1.57 N, THROUGH HOLE-STRAIGHT
ADTSM648N/KV KEYPAD SWITCH, SPST, MOMENTARY-TACTILE, 0.05A, 12VDC, 1.57 N, SURFACE MOUNT-STRAIGHT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-TS201SABP-050 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-TS201SABP-060 功能描述:IC PROCESSOR 600MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-TS201SABP-10X 制造商:Analog Devices 功能描述:
ADSP-TS201SABP-15X 制造商:Analog Devices 功能描述:
ADSP-TS201SABP-ENG 制造商:Analog Devices 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*