參數(shù)資料
型號(hào)： ADSP-TS101SKB2250X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 125 MHz, OTHER DSP, PBGA484
封裝： 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件頁數(shù)： 2/42頁
文件大?。?/td> 774K
代理商： ADSP-TS101SKB2250X
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
10
REV. PrE
PRELIMINARY TECHNICAL DATA
Filtering Reference Voltage and Clocks
Figure 5 shows a possible circuit for filtering VREF, SCLK_N, and
LCLK_N. This circuit provides the reference voltage for the
switching voltage, system clock, and local clock references.
Development Tools
The ADSP-TS101S is supported with a complete set of software
and hardware development tools, including Analog Devices’
emulators and VisualDSP++
2 development environment. The
same emulator hardware that supports other TigerSHARC DSPs
also fully emulates the ADSP-TS101S.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat-
ical functions. Two key points for these tools are:
Compiled TigerSHARC C/C++ code efficiency—the
compiler has been developed for efficient translation of
C/C++ code to TigerSHARC assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.
TigerSHARC family code compatibility—The assembler
has legacy features to ease the conversion of existing
previous TigerSHARC applications to the ADSP-
TS101S.
Debugging both C/C++ and assembly programs with the Visual-
DSP++ debugger, programmers can:
View mixed C/C++ and assembly code (interleaved
source and object information)
Insert break points
Set conditional breakpoints on registers, memory, and
stacks
Trace instruction execution
Perform linear or statistical profiling of program
execution
Fill, dump, and graphically plot the contents of memory
Debug source-level code
Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the TigerSHARC
development tools, including the syntax highlighting in the
VisualDSP++ editor. This capability lets programmers:
Control how the development tools process inputs and
generate outputs.
Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-TS101S processor to monitor and
control the target board processor during emulation. The
emulator provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonin-
trusive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the TigerSHARC processor family. Hardware
tools include TigerSHARC PC plug-in cards. Third Party
software tools include DSP libraries, real-time operating systems,
and block diagram design tools.
Designing an Emulator-Compatible DSP Board
(Target)
The White Mountain DSP (Product Line of Analog Devices,
Inc.) family of emulators are tools that every DSP developer
needs to test and debug hardware and software systems. Analog
Devices has supplied an IEEE 1149.1 JTAG Test Access Port
(TAP) on each JTAG DSP. The emulator uses the TAP to access
the internal features of the DSP, allowing the developer to load
code, set breakpoints, observe variables, observe memory, and
examine registers. The DSP must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices’ JTAG DSP and the
emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices’ JTAG DSP is a 14-
pin header, as shown in Figure 6. The customer must supply this
header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
square post header, set on 0.1"
0.1" spacing, with a minimum
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
Figure 5. VREF, SCLK_N, & LCLK_N filtering scheme
2 VisualDSP++ is a registered trademark of Analog Devices, Inc.
VDD_IO
VSS
VREF
SCLK_N
LCLK_N
R1
R2
C1
C2
R1: 2 k
SERIES RESISTOR
R2: 1.67 K
SERIES RESISTOR
C1: 1 F CAPACITOR (SMD)
C2: 1 nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’SPINS
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