參數(shù)資料
型號(hào)： ADSP-TS101SKB2250X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 125 MHz, OTHER DSP, PBGA484
封裝： 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件頁(yè)數(shù)： 38/42頁(yè)
文件大?。?/td> 774K
代理商： ADSP-TS101SKB2250X
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
5
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
mask register. All interrupts are fixed as either level-sensitive or
edge-sensitive, except the
IRQ3–0 hardware interrupts, which
are programmable.
The DSP distinguishes between hardware interrupts and
software exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and
a subtract in both computation blocks while it also branches to
another location in the program. Some key features of the instruc-
tion set include:
Enhanced instructions for communications infrastruc-
ture to govern Trellis Decoding (for example, Viterbi
and Turbo decoders) and Despreading via complex
correlations
Algebraic assembly language syntax
Direct support for all DSP, imaging, and video arith-
metic types, eliminating hardware modes
Branch prediction encoded in instruction, enables zero-
overhead loops
Parallelism encoded in instruction line
Conditional execution optional for all instructions
User defined partitioning between program and data
memory
On-Chip SRAM Memory
The ADSP-TS101S has 6M bits of on-chip SRAM memory,
divided into three blocks of 2M bits (64K words
× 32 bits). Each
block—M0, M1, and M2—can store program, data, or both, so
applications can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch.
The DSP’s internal and external memory is organized into a
unified memory map, which defines the location (address) of all
elements in the system, as shown in Figure 2.
The memory map is divided into four memory areas—host space,
external memory, multiprocessor space, and internal memory—
and each memory space, except host memory, is subdivided into
smaller memory spaces.
Each internal memory block connects to one of the 128-bit wide
internal buses—block M0 to bus MD0, block M1 to bus MD1,
and block M2 to bus MD2—enabling the DSP to perform three
memory transfers in the same cycle. The DSP’s internal bus
architecture provides a total memory bandwidth of 12G bytes per
second, enabling the core and I/O to access eight 32-bit data
words (256 bits) and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables:
DSP core and I/O access different memory blocks in the
same cycle
DSP core access all three memory blocks in parallel—one
instruction and two data accesses
Programmable partitioning of program and data memory
Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
Complete context switch in less than 20 cycles (80 ns)
External Port (Off-Chip Memory/Peripherals Interface)
The ADSP-TS101S’s external port provides the DSP’s interface
to off-chip memory and peripherals. The 4G word address space
is included in the DSP’s unified address space. The separate on-
chip buses—three 128-bit data buses and three 32-bit address
buses—are multiplexed at the external port to create an external
system bus with a single 64-bit data bus and a single 32-bit
address bus. The external port supports data transfer rates
of 800M bytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the lower
32 bits of the external data bus connect to even addresses, and
the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or slow
devices, host processors, and other memory-mapped peripherals
with variable access, hold, and disable time requirements.
Host Interface
The ADSP-TS101S provides an easy and configurable interface
between its external bus and host processors through the external
port. To accommodate a variety of host processors, the host
interface supports pipelined or slow protocols for accesses of the
host as slave. Each protocol has programmable transmission
parameters, such as idle cycles, pipe depth, and internal wait
cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the
BRST signal, the DSP increments the address
internally while the host continues to assert
BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The
BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts
BOFF, the DSP backs off the current
transaction and asserts
HBG and relinquishes the external bus.
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