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參數(shù)資料
| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
13
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
Table 4. LCLK Ratio
LCLKRAT2–0Ratio
000
(default)
2
001
2.5
010
3
011
3.5
100
4
101
5
110
6
111
Reserved
Table 5. Pin Definitions—External Port
Signal
Type
Description
ADDR31–0
1
I/O/T
Address Bus. The DSP issues addresses for accessing memory and peripherals on these
pins. In a multiprocessor system, the bus master drives addresses for accessing internal
memory or I/O processor registers of other ADSP-TS101Ss. The DSP inputs
addresses when a host or another DSP accesses its internal memory or I/O processor
registers.
DATA63–0
I/O/T
External Data Bus. The DSP drives and receives data and instructions on these pins.
Pull-up resistors on unused DATA pins are unnecessary.
RD2
I/O/T (pu)
Memory Read.
RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave,
RD is an input and indicates read
transactions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives
RD. RD changes concurrently with ADDR pins.
WRL2
I/O/T (pu)
Write Low.
WRL is asserted in two cases: When the ADSP-TS101S writes to an even
address word of external memory or to another external bus agent; and when the
ADSP-TS101S writes to a 32-bit zone (host, memory or DSP programmed to 32-bit
bus). An external master (host or DSP) asserts
WRL for writing to a DSP’s low word
of internal memory. In a multiprocessor system, the bus master drives
WRL. WRL
changes concurrently with ADDR pins. When the DSP is a slave,
WRL is an input
and indicates write transactions that access its internal memory or universal registers.
WRH2
I/O/T (pu)
Write High.
WRH is asserted when the ADSP-TS101S writes a long word (64 bits)
or writes to an odd address word of external memory or to another external bus agent
on a 64-bit data bus. An external master (host or another DSP) must assert
WRH for
writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system, the bus
master drives
WRH. WRH changes concurrently with ADDR pins. When the DSP is
a slave,
WRH is an input and indicates write transactions that access its internal
memory or universal registers.
ACK
I/O/T
Acknowledge. External slave devices can de-assert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers and other periph-
erals on the data phase. The DSP can de-assert ACK to add wait states to read accesses
of its internal memory. The ADSP-TS101S does not drive ACK during slave writes.
Therefore, an external (approximately 10 k
) pullup is required.
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
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| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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