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參數(shù)資料
| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
14
REV. PrE
PRELIMINARY TECHNICAL DATA
BMS2,3
O/T
(pu/pd)
Boot Memory Select.
BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses
BMS as a strap pin (EBOOT) for EPROM boot mode. When the
DSP is configured to boot from EPROM,
BMS is active during the boot sequence.
Pulldown enabled during
RESET (asserted); pullup enabled after RESET
(deasserted). In a multiprocessor system, the DSP bus master drives
BMS.For details
see Reset and Booting on page 9 and the EBOOT signal description in Table 14 on
MS1–02
O/T (pu)
Memory Select.
MS0 or MS1 is asserted whenever the DSP accesses memory banks
0 or 1 respectively.
MS1–0 are decoded memory address pins that change concurrently
with ADDR pins. When ADDR31:26 = 0b000010,
MS0 is asserted. When
ADDR31:26 = 0b000011,
MS1 is asserted. In multiprocessor systems, the master
DSP drives
MS1–0.
MSH2
O/T (pu)
Memory Select Host.
MSH is asserted whenever the DSP accesses the host address
space (ADDR31:28
≠ 0b0000). MSH is a decoded memory address pin that changes
concurrently with ADDR pins. In a multiprocessor system, the bus master DSP drives
MSH.
BR7–0
I/O
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to
arbitrate for bus mastership. Each DSP drives its own
BRx line (corresponding to the
value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight
DSPs, set the unused
BRx pins high.
ID2–0
I (pd)
Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order
in a multiprocessor system. These pins also indicate to the DSP which bus request
(
BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,
011 =
BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a
constant value during system operation and can change during reset only.
O (pd)
Bus Master. The current bus master DSP asserts
BM. For debugging only. At reset
this is a strap pin. For more information, see Table 14 on page 19.
BOFF
I
Back Off. A deadlock situation can occur when the host and a DSP try to read from
each other’s bus at the same time. When deadlock occurs, the host can assert
BOFF
to force the DSP to relinquish the bus before completing its outstanding transaction.
BUSLOCK2
O/T (pu)
Bus Lock Indication. Provides an indication that the current bus master has locked
the bus.
BRST2
I/O/T (pu)
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automati-
cally while
BRST is asserted.
HBR
I
Host Bus Request. A host must assert
HBR to request control of the DSP’s external
bus. When
HBR is asserted in a multiprocessing system, the bus master relinquishes
the bus and asserts
HBG once the outstanding transaction is finished.
HBG2
I/O/T (pu)
Host Bus Grant. Acknowledges
HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master DSP three-states the
ADDR31–0, DATA63–0,
MSH, MSSD, MS1–0, RD, WRL, WRH, BMS, BRST,
FLYBY, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM and HDQM pins, and
the DSP puts the SDRAM in self-refresh mode. The DSP asserts
HBG until the host
deasserts
HBR. In multiprocessor systems, the current bus master DSP drives HBG,
and all slave DSPs monitor it.
Table 5. Pin Definitions—External Port (continued)
Signal
Type
Description
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
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