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參數(shù)資料
| 型號： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
30
REV. PrE
PRELIMINARY TECHNICAL DATA
I
DDINIDLE—VDD supply current for idle activity
Idle activity is the core executing the IDLE instruction
only with no DMA or interrupts.
I
DDINIDLELP—VDD supply current for idle low power
activity
Idle Low Power activity is the core executing the
IDLE(LP) instruction only with no DMA or interrupts.
External Power Calculation
The external power on VDD_IO is consumed by the switching of
output pins and is system dependent. For each unique group of
pins, the magnitude of power consumed depends on:
The number of output pins that switch during each
cycle, O
Their load capacitance, C
Their voltage swing, V
DD_IO
The maximum frequency at which they can switch, f
and is calculated by the formula in Figure 17.
The load capacitance should include the input capacitance of
each connected device as well as the DPS's own input capacitance
(CIN) For additional accuracy trace capacitance should be
included if possible. The switching frequency includes driving
the load high and then back low. Address and data pins can drive
high and low at a maximum rate of SCLK.
For example, estimate PEXT for the external port pins with the
following assumptions:
System consists of one ADSP-TS101S with one bank of
external memory (64-bit).
Two 1M × 32 SDRAM chips are used, each with a load
of 5 pF per pin (trace capacitance neglected for this
example).
Continuous burst of quad-word (128-bit) writes occur
every cycle at a rate of SCLK, with 50% of the data pins
switching (represents random data).
Address increments sequentially on transaction boundary
(every quad-word). For sequential addressing, the
number of address bits switching approaches 2-bits.
Control switches for refresh and page boundaries.
SCLK = 100Mhz (bus cycle time).
The PEXT equation is calculated for each class of pins that can
drive as shown in Table 23.
Test Conditions
The test conditions for timing parameters appearing in ADSP-
TS101S—Specifications on page 20 include output disable time,
output enable time, and capacitive loading. The timing specifi-
cations for the DSP apply for the voltage reference levels in
Figure 17. External Power PEXT Calculation
P
EXT
OCV
DD_IO
2
×
f
×
=
Table 23. External Power PEXT Calculation
Pin Type
# of Pins
% Switching
C
VDD_IO
2
f= PEXT
Data
64
50
(5 pF + CIN)
10.9 V
2
50 MHz
= TBD W
Address
32
6.25
(10 pF + CIN)
10.9 V
2
25 MHz
= TBD W
Control
8
50
(10 pF + CIN)
10.9 V
2
250 KHz
= TBD W
PEXT=TBD W
Figure 18. Voltage reference levels for AC measurements
(except output enable/disable)
INPUT
OR
OUTPUT
1.5V
Figure 19. Output Enable/Disable
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V
VOL (MEASURED) + V
tMEASURED_DIS
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
tMEASURED_ENA
tRAMP
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| ADSP-TS201SABP-060 | 功能描述:IC PROCESSOR 600MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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