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參數(shù)資料
| 型號(hào)： | ADSP-TS101SKB2250X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封裝： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 41/42頁 |
| 文件大?。?/td> | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
8
REV. PrE
PRELIMINARY TECHNICAL DATA
DMA Controller
The ADSP-TS101S’s on-chip DMA controller, with 14 DMA
channels, provides zero-overhead data transfers without
processor intervention. The DMA controller operates indepen-
dently and invisibly to the DSP’s core, enabling DMA operations
to occur while the DSP’s core continues to execute program
instructions.
The DMA controller performs DMA transfers between
internal memory and external memory and memory-
mapped peripherals, the internal memory of other DSPs on
a common bus, a host processor, or link port I/O; between
external memory and external peripherals or link port I/O;
and between an external bus master and internal memory
or link port I/O. The DMA controller performs the following
DMA operations:
External port block transfers. Four dedicated bidirec-
tional DMA channels transfer blocks of data between the
DSP’s internal memory and any external memory or
memory-mapped peripheral on the external bus. These
transfers support master mode and handshake mode
protocols.
Link port transfers. Eight dedicated DMA channels (four
transmit and four receive) transfer quad-word data only
between link ports and between a link port and internal
or external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.
AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus
master to internal memory or to link port I/O. These
transfers only use slave mode protocol, and an external
bus master must initiate the transfer.
The DMA controller provides these additional features:
Flyby transfers. Flyby operations only occur through the
external port (DMA channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to
transfer data from one external device to another through
external memory. During a transaction, the DSP relin-
quishes the external data bus; outputs addresses, memory
selects (
MS1–0) and the FLYBY, IOEN, and RD/WR
strobes; and responds to ACK.
DMA chaining. DMA chaining operations enable appli-
cations to automatically link one DMA transfer sequence
to another for continuous transmission. The sequences
can occur over different DMA channels and have different
transmission attributes.
Two-dimensional transfers. The DMA controller can
access and transfer two-dimensional memory arrays on
any DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.
Link Ports
The DSP’s four link ports provide additional eight-bit bidirec-
tional I/O capability. With the ability to operate at a double data
rate—latching data on both the rising and falling edges of the
clock—running at 125 MHz, each link port can support up to
250M bytes per second, for a combined maximum throughput
of 1G bytes per second.
The link ports provide an optional communications channel that
is useful in multiprocessor systems for implementing point-to-
point interprocessor communications. Applications can also use
the link ports for booting.
Each link port has its own double-buffered input and output
registers. The DSP’s core can write directly to a link port’s
transmit register and read from a receive register, or the DMA
controller can perform DMA transfers through eight (four
transmit and four receive) dedicated link port DMA channels.
Each link port has three signals that control its operation.
LxCLKOUT and LxCLKIN implement clock/acknowledge
handshaking. LxDIR indicates the direction of transfer and is
used only when buffering the LxDAT signals. An example appli-
cation would be using differential low-swing buffers for long
twisted-pair wires. LxDAT provides the 8-bit data bus
input/output.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port trans-
fers), the size of data packets, and the speed at which bytes are
transmitted.
Under certain conditions, the link port receiver can initiate a
token switch to reverse the direction of transfer; the transmitter
becomes the receiver and vice versa.
Timer and General-Purpose I/O
The ADSP-TS101S has a timer pin (
TMR0E) that generates
output when a programmed timer counter has expired and four
programmable general-purpose I/O pins (FLAG3–0) that can
function as either single-bit input or output. As outputs, these
pins can signal peripheral devices; as inputs, they can provide the
test for conditional branching.
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| ADSP-TS201SABP-050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS201SABP-060 | 功能描述:IC PROCESSOR 600MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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