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CHAPTER 8 JTAG BOUNDARY SCAN
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8.2.4 Boundary Scan Register
The boundary scan register is configured between the external pins and internal logic circuits of the
μ
PD98405. When this register is selected, data is latched or loaded according to instructions received from
the TAP controller.
While the TAP controller is in the Shift-DR state, if the boundary scan register is selected, data is output to
the JDO pin, starting from the LSB, at the falling edge of the clock input to the JCK pin.
8.3 PIN FUNCTIONS
8.3.1 JCK Pin
The JCK pin is used to supply a clock signal to the JTAG boundary scan circuit (bypass register, instruction
register, TAP controller). The configuration is such that this clock signal is prevented from being supplied to
other internal circuits of the
μ
PD98405.
8.3.2 JMS Pin
The input to the JMS pin is latched at the rising edge of the clock input to the JCK pin, to define the
operation of the TAP controller.
8.3.3 JDI Pin
The JDI pin is used to input data to the registers of the JTAG boundary scan circuit.
8.3.4 JDO Pin
The JDO pin is used to output data from the registers of the JTAG boundary scan circuit. The output is
modified at the falling edge of the clock being input to the JCK pin. Furthermore, the JDO pin can assume any
of three states, as directed by the TAP controller.
8.3.5 JRST_B Pin
The JRST_B pin is used to asynchronously initialize the TAP controller. Upon the input of the reset signal,
the normal operating mode of the
μ
PD98405 is set, and the boundary register enters the non-operating state.