17
LIST OF TABLES (1/2)
Table No. Title Page
4-1
Bus Parity Mode Select Bits..........................................................................................57
4-2
Selecting Burst Size to Be Enabled...............................................................................62
4-3
DMA Transfer by
μ
PD98405 .........................................................................................62
4-4
Burst Size Being Used...................................................................................................63
4-5
Burst Transfer Transition...............................................................................................65
4-6
Configuration Register...................................................................................................75
4-7
DMA Transfer Burst Sizes.............................................................................................86
4-8
EEPROM Commands....................................................................................................97
4-9
EEPROM Format...........................................................................................................98
5-1
μ
PD98405 Mailbox Operation .....................................................................................126
5-2
Function of Packet Descriptor .....................................................................................130
5-3
Scheduler Register Bit Functions................................................................................150
5-4
Data Supported by the
μ
PD98405 Transmit Function.................................................167
5-5
Types of Receive Data and Pools Used......................................................................174
5-6
Errors Which May Occur for All of the First, Intermediate,
and Last Cells of the Packet........................................................................................196
5-7
Error Which Takes Precedence upon Occurrence of Multiple Errors .........................196
5-8
Descriptions of RM Cell Fields ....................................................................................215
5-9
ABR Parameters..........................................................................................................216
5-10
Commands ..................................................................................................................235
5-11
L Bit State Transition due to Register Access.............................................................238
5-12
Commands for Which an Indication Is Issued as a Response/Not Issued..................241
5-13
L Bit State Transition due to Register Read-Access...................................................242
6-1
Frame Synchronization Pattern...................................................................................266
6-2
Synchronization Byte...................................................................................................266
6-3
OCD Bit........................................................................................................................268
6-4
HEC Error Correction Mode ........................................................................................269
6-5
Transmitting an Alarm .................................................................................................271
6-6
Dummy Error Frames..................................................................................................274
6-7
Alarms and Failures.....................................................................................................275
6-8
Performance Cause Register (PCR Register).............................................................277