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13
LIST OF FIGURES (1/4)
Figure No. Title Page
3-1
Functions of
μ
PD98405.................................................................................................45
3-2
Outline of
μ
PD98405 System........................................................................................47
3-3
PDU Format of AAL-5....................................................................................................48
3-4
User Network Interface (UNI) of Cell Structure .............................................................49
3-5
Outline of Frame Transmission Function.......................................................................53
3-6
Outline of Frame Reception Function............................................................................53
4-1
Bus Interface Signals.....................................................................................................55
4-2
Differences in Uses of Pins between Byte and Word Parity Modes..............................57
4-3
1-Word Write DMA Cycle Timing...................................................................................59
4-4
1-Word Read DMA Cycle Timing ..................................................................................59
4-5
ABRT_B Signal Input Timing.........................................................................................61
4-6
Burst Write Cycle Timing...............................................................................................63
4-7
Transmit Cell Data Byte Alignment (in Little Endian Format)........................................66
4-8
DMA Write Transfer to Receive Buffer in Byte Units.....................................................67
4-9
Slave Access Timing .....................................................................................................69
4-10
Input Timing of SEL_B and ASEL_B Signals................................................................71
4-11
Little Endian Format ......................................................................................................72
4-12
Big Endian Format.........................................................................................................72
4-13
Layout of Configuration Register...................................................................................74
4-14
Slave Transaction Timing..............................................................................................77
4-15
Master Transaction Timing............................................................................................79
4-16
Fast Back-to-Back Transaction Timing..........................................................................80
4-17
64-Bit Bus Transaction Timing ......................................................................................82
4-18
Time-Out Termination (Latency Timer: 8) ....................................................................84
4-19
Master Abort Termination (No Target Responds to DEVSEL_B) .................................84
4-20
Per-VC Queuing Block Diagram....................................................................................87
4-21
Example of AD Bit Function...........................................................................................89
4-22
Burst Size Transition When AD = 0 (12-Word Transfer)...............................................90
4-23
Burst Size Transition When AD = 0 (Multi-Cell Transfer (5 Cells)) ...............................91
4-24
Example of Storing Cell Data into a Buffer on a Byte Boundary...................................92
4-25
Transaction Termination by Retry Timer (Retry Timer Register: 2) .............................94
4-26
Transaction Termination by TRDY Timer (TRDY Timer Register: 16).........................94
4-27
Expansion ROM Interface Timing..................................................................................95