![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_311.png)
CHAPTER 7 REGISTERS
311
(6) T1R (T1 time)
Address:
300H
Access mode: Read/write
T1R sets the user-specified time during which the reception of one packet is enabled. The time is defined
by the high-order 16 bits of the 32-bit value, in units of system clock cycles. Set the low-order 16 bits to
"0000H." The default value for this register is "FFFFH" after a reset. It is not possible to write to bits 31 to
16. Upon a read, 0 is returned.
31
0
T1 VALUE
16
15
- 0 -
(7) VRR (VPI/VCI reduction register)
Address:
301H
Access mode: Read/write
The VRR register is used to reduce the 24-bit pattern of the received VPI/VCI value to the 16 bits of an
internal logic code. Set the 4-bit "SHIFT" parameter and 16-bit "MASK" parameter. Setting a VFM bit
enables filtering of received VPI/VCI values.
For an explanation of the conversion algorithm, see
Section 5.5.4
.
The MSB bit is used as the bit of the "global shutdown" command. When the host writes 1 to this bit, the
μ
PD98405 stops all reception processing currently being executed, sets the RD bit of the GSR register to
1, and issues an interrupt provided it is not masked. The default value of this register is "0000FFFFH" after
a reset. It is not possible to write to bits 29 to 20. Upon a read, 0 is returned.
31
0
MASK
0
16
15
20
19
SHIFT
30
SDM VFM
29
SDM: Global shutdown bit
0: Normal operation
1: Execution of global shutdown
VFM:
VPI/VCI filtering mode
0: Enables the VPI/VCI filtering function
1: Disables the VPI/VCI filtering function