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CHAPTER 7 REGISTERS
352
(31) Performance counter overflow cause register 1 (PCOCR1)
This register is used to indicate the cause of a performance counter overflow.
Register name
D7
D6
D5
D4
D3
D2
D1
D0
Address
Default
R/W
PCOCR1
0
0
B1EC B2EC B3EC LFBC PFBC
FJC
20H
00H
R
Field
Function
Default value
Used to indicate whether a B1E counter overflow has occurred.
1
Indicates that the B1E counter has overflowed.
0
Indicates that the B1E counter has not overflowed.
Used to indicate whether a B2E counter overflow has occurred.
1
Indicates that the B2E counter has overflowed.
0
Indicates that the B2E counter has not overflowed.
Used to indicate whether a B3E counter overflow has occurred.
1
Indicates that the B3E counter has overflowed.
0
Indicates that the B3E counter has not overflowed.
Used to indicate whether an L-FEBE counter overflow has occurred.
1
Indicates that the L-FEBE counter has overflowed.
0
Indicates that the L-FEBE counter has not overflowed.
Used to indicate whether a P-FEBE counter overflow has occurred.
1
Indicates that the P-FEBE counter has overflowed.
0
Indicates that the P-FEBE counter has not overflowed.
Used to indicate whether an FJ counter overflow has occurred.
1
Indicates that the FJ counter has overflowed.
0
Indicates that the FJ counter has not overflowed.
D5: B1EC
0
D4: B2EC
0
D3: B3EC
0
D2: LFBC
0
D1: PFBC
0
D0: FJC
0
Remarks 1
. When this register is read, 0 is returned for the high-order two bits. The high-order two bits
cannot be written.
2
. While any one bit of this register is set to 1, the PCO bit of the PICR register (address: 06H)
is also set to 1.
3
. This register is cleared upon being read.