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參數(shù)資料
| 型號(hào)： | μPD98411 |
| 廠商： | NEC Corp. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大小： | 28K |
| 代理商： | ΜPD98411 |
The μPD98411 integrates the quad TC sublayers function of ATM over SONET STS-3c/SDH-STM-1
frames, as specified by the ATM Forum specifications. The μPD98411 maps an ATM cell passed from
an ATM layer to the payload of a 155-bps SONET/SDH frame and then transmits the cell to the
Physical Media Dependent (PMD) sublayer, a reception function that first separates ATM cells of the
SONET/SDH frame received from the PMD device and then transmits them to the ATM layer. The
μPD98411 combines transmission and reception functions of four ports into a single chip ideally suited
for use in ATM multiplexers, ATM switches, and other equipment used to configure the ATM network.
In addition, the μPD98411 incorporates independent clock recovery functions for each port to extract a
synchronous clock for reception of receive data from the bit stream and a clock synthesis function to
generate a clock for transmission.
μP D 9 8 4 1 1 A T M Q U A D S O N E T F R A M E R
( N E A S C O T-P 4 0
T M
)
B L O C K
D I A G R A M
Rx Framer Block
Rx Timing Generate
BIP Generate
Descramble
Overhead Extract
Port0
98YL-0162B (6/98)
P/S
Tx FrRx Framer Block
Tx FIFO
Tx ATRx ATM Cell Processor Block
P
(
A
Tx Framer Block
Tx Timing Generate
P
(
Scramble
BIP Generate
Overhead Setup
Rx ATM Cell Processor Block
HEC Veri./Corr.
Cell Descramble
Cell Delineation
Idle Cell Drop
Tx ATM Cell Processor Block
HEC Generate
Cell Mapping Idle Cell Insertion
Cell Scramble
Rx FIFO
(8 cells)
Tx FIFO
(8 cells)
Clock
Recov.
S/P
Clock
Recov.
Port1
S/P
Tx FrRx Framer Block
Tx FIFO
Tx ATRx ATM Cell Processor Block
P
(
Clock
RecP/S
Port1
S/P
Clock Synthesizer
JTAG
Clock
RecP/S
S/P
Management Interface
Address: 9 bits
Data:
UTOPIA level2 Management Interface
"Rd, Wr and Rdy type", "DS, R/W Dtack type" selectable
8 bits
APS:
UTOPIA:
OAM:
Automatic Protection Switching
Universal Test and Operation PHY Interface for ATM
Operation, Administration, Maintenance
UTOPIA level2 Multi-PHY Interface
16-bit width/8-bit width/8-bit width x 2
modes selectable
155.52 MHz
PECL Serial Interface
Rx Framer Block
Rx FIFO
Rx ATM Cell Processor Block
Rx FIFO
P/S
Tx Framer Block
Rx FIFO
Tx FIFO
Tx ATM Cell Processor Block
Port1
P
(
OAM Sequencer
Mode
Registers
Mode
Registers
INT Cause
Registers
Tx/Rx Overhead
Registers
Performance
Registers
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