![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_19.png)
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CHAPTER 1 OVERVIEW
The
μ
PD98405 is a high performance ATM segmentation and reassembly chip (SAR chip). It features a PCI
bus interface, a SONET/SDH 155-Mbps framer, clock recovery, and supports the ABR function in hardware.
The chip conforms to the ATM Forum recommendations and implements the required AAL-5 SAR sublayer,
ATM layer, and TC sublayer functions.
1.1 FEATURES
Conforms to the ATM Forum recommendations.
The PCI bus and general-purpose bus are supported as host bus interfaces.
- Built-in PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to the PCI Specification Revision 2.1
- General-purpose bus interface (5/3.3 V, 32 bits, 33 MHz)
Implements the required AAL-5 SAR sublayer, ATM layer, and TC sublayer functions.
Support of AAL-5 processing in hardware
Software support of non-AAL-5 traffic
Implements a SONET STS-3c/SDH STM-1 155-Mbps framer function.
Implements clock recovery/clock synthesizer functions.
Supports up to 32K virtual channels (VCs).
16 VBR traffic shapers for transmission scheduling
Hardware support of CBR/VBR/ABR/UBR service
Supports multi-cell burst transfer for transmission and reception.
Implements an MIB counter.
Supports the LAN emulation function.
Receive FIFO which can contain up to 96 cells
UTOPIA Level-1 interface for an external PHY layer device
0.35-
μ
m CMOS technology and 5/3.3-V power supply
- Bus interface 5 V:
5/3.3-V power supply
- Bus interface 3.3 V: Single 3.3-V power supply
304-pin plastic QFP
1.2 ORDERING INFORMATION
Part Number
Package
μ
PD98405GL-PMU
304-pin plastic QFP (0.5 mm, fine pitch) (40 x 40 mm)
Not all devices/types available in every country. Please check with local NEC representative for availability and
additional information.