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CHAPTER 7 REGISTERS
336
(15) B2 error count register (B2ECT)
7
0
Address
Default
R/W
B2ECT
0EH
00H
R
B2EC[1:0] = 10
B2EC[1:0] = 01
B2EC[1:0] = 00
23
19
16 15
8
7
0
B2ECNTR
0
0
0
0
The SMP bit is set to 1
19
16 15
8
7
0
B2E counter
This is a window register that is used to read the contents of the 20-bit
B2ECNTR
register by reading eight
bits, eight bits, and four bits, three times. First, the low-order eight bits (
B2ECNTR[7:0]
) are read, then the
middle eight bits (
B2ECNTR[15:8]
), and finally the high-order four bits (
B2ECNTR[19:16]
). Which of the
low-order, middle, or high-order bits is read is indicated by the
B2EC1
and
B2EC0
bits of the
PCPR1
register (address: 19H). For each of these bits, the default value is 00. Each time the
B2ECT
register is
read, the value of these bits changes in the order of 00 -> 01 -> 10 -> 00 -> 01.
B2ECNTR
is a load register that is used to sample (store) the value of the B2 error counter. By setting the
SMP
bit of the
PCSR
register (address: 1BH) to 1, the value of the
B2E counter
is stored into the
B2ECNTR register
. This value indicates the number of B2 errors that have occurred since the contents of
the
B2E counter
were last sampled. The value stored into the
B2ECNTR
register is held until the
B2E
counter
is next sampled.
Sampling the contents of the
B2E counter
causes the counter to be cleared to 0. The counter is also
cleared to 0 when the
B2EC
bit of the
PCIR1
register (address: 1CH) is set to 1.
When the value of the counter is all F, the
B2EC
bit of the
PCOCR1
register (address: 20H) is set to 1 to
indicate a counter overflow being detected. Also, the
PCO
bit of the
PICR
register (address: 06H) is set to
1, thus causing an interrupt. After the occurrence of an overflow, the
B2E counter
again starts to count up
from 0.