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CHAPTER 7 REGISTERS
342
(21) FIFO full count register (FULCT)
7
0
Address
Default
R/W
FULCT
14H
00H
R
FULC[1:0] = 10
FULC[1:0] = 01
FULC[1:0] = 00
23
19
16 15
8
7
0
FULCNTR
0
0
0
0
The SMP bit is set to 1
19
16 15
8
7
0
FIFO full counter
This is a window register that is used to read the contents of the 20-bit
FULCNTR
register by reading eight
bits, eight bits, and four bits, three times. First, the low-order eight bits (
FULCNTR[7:0]
) are read, then the
middle eight bits (
FULCNTR[15:8]
), and finally the high-order four bits (
FULCNTR[19:16]
). Which of the
low-order, middle, or high-order bits is read is indicated by the
FULC1
and
FULC0
bits of the
PCPR2
register (address: 1AH). For each of these bits, the default value is 00. Each time the
FULCT
register is
read, the value of these bits is automatically changed in the order of 00 -> 01 -> 10 -> 00 -> 01.
FULCNTR
is a load register that is used to sample (store) the value of the FIFO full counter. By setting the
SMP
bit of the
PCSR
register (address: 1BH) to 1, the value of the
FIFO full counter
is stored into the
FULCNTR
register. This value indicates the number of cells that have been discarded as a result of the
FIFO full since the contents of the
FIFO full counter
were last sampled. The value stored into the
FULCNTR
register is held until the
FIFO full counter
is next sampled.
Sampling the contents of the
FIFO full counter
causes the counter to be cleared to 0. The counter is also
cleared to 0 when the
FULC
bit of the
PCIR2
register (address: 1DH) is set to 1.
When the value of the counter is all F, the
FULC
bit of the
PCOCR2
register (address: 21H) is set to 1 to
indicate a counter overflow being detected. Also, the
PCO
bit of the
PICR
register (address: 06H) is set to
1, thus causing an interrupt. After the occurrence of an overflow, the
FIFO full counter
again starts to
count up from 0.