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CHAPTER 7 REGISTERS
354
(33) Performance counter overflow mask register 1 (PCOMR1)
This register is used to set masking of the cause of an overflow, as indicated by the PCOCR1 register
(address: 20H). When masking is applied, the PCO bit of the PICR register (address: 06H) is not set
even when the cause of the overflow is set.
Register name
D7
D6
D5
D4
D3
D2
D1
D0
Address
Default
R/W
PCOMR1
0
0
B1EC B2EC B3EC LFBC PFBC
FJC
22H
00H
R/W
Field
Function
Default value
Used to set masking of the occurrence of a B1E counter overflow.
1
Does not mask the occurrence of a B1E counter overflow.
0
Masks the occurrence of a B1E counter overflow.
Used to set masking of the occurrence of a B2E counter overflow.
1
Does not mask the occurrence of a B2E counter overflow.
0
Masks the occurrence of a B2E counter overflow.
Used to set masking of the occurrence of a B3E counter overflow.
1
Does not mask the occurrence of a B3E counter overflow.
0
Masks the occurrence of a B3E counter overflow.
Used to set masking of the occurrence of an L-FEBE counter overflow.
1
Does not mask the occurrence of an L-FEBE counter overflow.
0
Masks the occurrence of an L-FEBE counter overflow.
Used to set masking of the occurrence of a P-FEBE counter overflow.
1
Does not mask the occurrence of a P-FEBE counter overflow.
0
Masks the occurrence of a P-FEBE counter overflow.
Used to set masking of the occurrence of an FJ counter overflow.
1
Does not mask the occurrence of an FJ counter overflow.
0
Masks the occurrence of an FJ counter overflow.
D5: B1EC
0
D4: B2EC
0
D3: B3EC
0
D2: LFBC
0
D1: PFBC
0
D0: FJC
0
Remark
When this register is read, 0 is returned for the high-order two bits. The high-order two bits
cannot be written.