![](http://datasheet.mmic.net.cn/380000/-PD98405_datasheet_16745025/-PD98405_290.png)
CHAPTER 7 REGISTERS
290
Address W (H) Address B (H)
Register
Function
R/W
R/W
Default value
1E
78
MTA2
Mailbox 2 tail address
Not defined
1F
7C
MTA3
Mailbox 3 tail address
R/W
Not defined
20
80
MWA0
Mailbox 0 write address
R/W
Not defined
21
22
23
24
25
26
27
28
84
88
8C
90
94
98
9C
A0
MWA1
MWA2
MWA3
RCC
TCC
RUEC
RIDC
PBAH
Mailbox 1 write address
Mailbox 2 write address
Mailbox 3 write address
Receive cell counter
Transmit cell counter
Invalid VPI/VCI receive cell error counter
Internally discarded receive cell counter
PCI base address high
R/W
R/W
R/W
R
R
R
R
R/W
Not defined
Not defined
Not defined
00H
00H
00H
00H
00H
(2) Indirect address registers
To access the indirect address registers, the Indirect_Access command is used.
Scheduler registers
Address (H)
0 - F
10 - 1F
20 - 2F
30 - 3F
40 - 4F
50
51
Register
I, M
X
Y
P, C, p, c
Pri & Status
Priority
Priority
Function
R/W
Default value
I and M entry of schedulers 0 through 15
X entry of schedulers 0 through 15
Y entry of schedulers 0 through 15
P, C, p, c entries of schedulers 0 through 15
Priority and status of schedulers 0 through 15
ABR scheduler priority (in-rate)
ABR scheduler priority (out-of-rate)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
Other registers
Address (H)
100
101
102 - 111
200
201
300
301
302
305
306
307
308
400
401
402
403
Register
TOS
SCR
SPE
ALA
PMA
T1R
VRR
TSR
HTU
HTL
MAU
MAL
APR
TBW
TTH0
TTH1
Function
R/W
Default value
Control memory address of top of stack
Shaper control register
Shaper pointer entries 0 through 15
Control memory start address of ABR lookup table
Control memory start address of receive pool
T1 register
VPI/VCI reduction register/global shutdown
Time stamp register
Upper 32 bits of hashing table register
Lower 32 bits of hashing table register
Upper 32 bits of MAC address
Lower 16 bits of MAC address
ABR parameter register
Total bandwidth register
Time threshold register 1
Time threshold register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000H
00000000H
00000000H
00000000H
00000000H
0000FFFFH
0000FFFFH
00000000H
00000000H
00000000H
00000000H
00000000H
89F9FF14H
000092C7H
00007FFFH
00007FFFH