
PRELIMINARY
XRT86SH328
85
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT [7:0] -
B1 Byte Error Count (Bits 23 through 16)
This RESET-upon-READ register, along with Receive STS-1/STS-3 Transport - B1 Byte Error Count Register - Bytes
3, 1 and 0, function as a 32 bit counter, which is incremented anytime the Receive STS-1/STS-3 TOH Processor block
detects a B1 byte error.
N
OTES
:
1.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B1 byte errors on a per-bit
basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming
STS-1/STS-3 frame) that are in error.
2.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B1 byte errors on a per-frame
basis, then it will increment this 32 bit counter each time that it receives an STS-1/STS-3 frame that contains
an erred B1 byte.
BIT [7:0] - B1 Byte Error Count - (Bits 15 through 8)
This RESET-upon-READ register, along with Receive STS-1/STS-3 Transport - B1 Byte Error Count Register - Bytes
3, 2 and 0, function as a 32 bit counter, which is incremented anytime the Receive STS-1/STS-3 TOH Processor block
detects a B1 byte error.
N
OTES
:
1.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B1 byte errors on a per-bit
basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming
STS-1/STS-3 frame) that are in error
2.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B1 byte errors on a per-frame
basis, then it will increment this 32 bit counter each time that it receives an STS-1/STS-3 frame that contains
an erred B1 byte.
BIT [7:0] - B1 Byte Error Count - LSB
This RESET-upon-READ register, along with Receive STS-1/STS-3 Transport - B1 Byte Error Count Register - Bytes
3 through 1, function as a 32 bit counter, which is incremented anytime the Receive STS-1/STS-3 TOH Processor block
detects a B1 byte error.
N
OTES
:
1.
basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming
STS-1/STS-3 frame) that are in error.
2.
If the Receive STS-1/STS-3 TOH Processor block is configured to count B1 byte errors on a per-frame
basis, then it will increment this 32 bit counter each time that it receives an STS-1/STS-3 frame that contains
an erred B1 byte.
If the Receive STS-1/STS-3 TOH Processor Block is configured to count B1 byte errors on a per-bit
T
ABLE
84: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- B1 B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
0212)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Byte_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
85: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- B1 B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0213)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Byte_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0