
PRELIMINARY
XRT86SH328
119
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
an NDF Pointer event.
`
0 - Disables the Detection of NDF Pointer interrupt.
`
1 - Enables the Detection of NDF Pointer interrupt.
BIT 1 - Change of LOP-P Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change in LOP (Loss of Pointer) Condition interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either
of the following events.
When the Receive STS-1 POH Processor block declares the LOP-P defect condition condition.
When the Receive STS-1 POH Processor block clears the LOP-P defect condition.
`
0 - Disable the Change of LOP-P Defect Condition Interrupt.
`
1 - Enables the Change of LOP-P Defect Condition Interrupt.
N
OTE
:
The user can determine the current state of the LOP-P Defect condition by reading out the contents of BIT 1
(LOP-P Defect Declared) within the Receive STS-1 Path - SONET Receive POH Status - Byte 0 (Address
Location= 0x0287).
BIT 0 - Change of AIS-P Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of AIS-P (Path AIS) Defect Condition
interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt in response to either
of the following events.
When the Receive STS-1 POH Processor block declares the AIS-P Defect condition.
When the Receive STS-1 POH Processor block clears the AIS-P Defect condition.
`
0 - Disables the Change of AIS-P Defect Condition Interrupt.
`
1 - Enables the Change of AIS-P Defect Condition Interrupt.
N
OTE
:
The user can determine the current state of the AIS-P Defect Condition by reading out the contents of BIT 0
(AIS-P Defect Declared) within the Receive STS-1 Path - SONET Receive POH Status - Byte 0 (Address
Location= 0x0287).
BIT 7 - Unused
BIT [6:4] - Accepted RDI-P Value
These READ-ONLY bit-fields contain the value of the most recently accepted RDI-P (e.g., bits 5, 6 and 7 within the G1
byte) value that has been accepted by the Receive STS-1 POH Processor block.
N
OTE
:
A given RDI-P value will be accepted by the Receive STS-1 POH Processor block, if this RDI-P value has been
consistently received in RDI-P THRESHOLD[3:0] number of STS-1/STS-3 frames.
BIT [3:0] - RDI-P Threshold[3:0]
These READ/WRITE bit-fields are used to defined the RDI-P Acceptance Threshold for the Receive STS-1 POH
Processor Block.
The RDI-P Acceptance Threshold is the number of consecutive STS-1/STS-3 frames, in which the Receive STS-1 POH
Processor block must receive a given RDI-P value, before it accepts or validates it.
The most recently accepted RDI-P value is written into the RDI-P ACCEPT[2:0] bit-fields, within this register.
T
ABLE
140: R
ECEIVE
STS-1 P
ATH
- SONET R
ECEIVE
RDI-P R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0293)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RDI-P_ACCEPT[2:0]
RDI-P THRESHOLD[3:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0