
XRT86SH328
PRELIMINARY
118
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT 7 - Detection of B3 Byte Error Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of B3 Byte Error Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects
a B3-byte error in the incoming STS-1/STS-3 data-stream.
`
0 - Disables the Detection of B3 Byte Error interrupt.
`
1 - Enables the Detection of B3 Byte Error interrupt.
BIT 6 - Detection of New Pointer Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of New Pointer interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a
new pointer value in the incoming STS-1/STS-3 frame.
N
OTE
:
:Pointer Adjustments with NDF will not generate this interrupt.
`
0 - Disables the Detection of New Pointer Interrupt.
`
1 - Enables the Detection of New Pointer Interrupt.
BIT 5 - Detection of Unknown Pointer Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of Unknown Pointer interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects a
Pointer Adjustment that does not fit into any of the following categories.· An Increment Pointer.· A Decrement Pointer·
An NDF Pointer· AIS Pointer· New Pointer.
`
0 - Disables the Detection of Unknown Pointer Interrupt.
`
1 - Enables the Detection of Unknown Pointer Interrupt.
BIT 4 - Detection of Pointer Decrement Interrupt Enable
This READ/WRITE bit-field is used to enable or disable the Detection of Pointer Decrement Interrupt.
If this interrupt is enabled, then the Receive STS-1/STS-3 TOH Processor block will generate an interrupt anytime it
detects a Pointer-Decrement event.
`
0 - Disables the Detection of Pointer Decrement Interrupt.
`
1 - Enables the Detection of Pointer Decrement Interrupt.
BIT 3 - Detection of Pointer Increment Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of Pointer Increment Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects
a Pointer Increment event.
`
0 - Disables the Detection of Pointer Increment Interrupt.
`
1 - Enables the Detection of Pointer Increment Interrupt.
BIT 2 - Detection of NDF Pointer Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of NDF Pointer Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will generate an interrupt anytime it detects
T
ABLE
139: R
ECEIVE
STS-1 P
ATH
- SONET R
ECEIVE
P
ATH
I
NTERRUPT
E
NABLE
- B
YTE
0 (A
DDRESS
L
OCATION
=
0
X
028F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
B3 Byte
ErrorInter-
ruptEnable
Detection of
New Pointer
Interrupt
Enable
Detection of
Unknown
Pointer Inter-
rupt Enable
Detection of
Pointer Dec-
rement Inter-
rupt Enable
Detection of
Pointer
IncrementIn-
terrupt
Enable
Detection of
NDF Pointer-
Interrupt
Enable
Change of
LOP-P
DefectCondi-
tion Interrupt
Enable
Change of
AIS-P
DefectCondi-
tionInterrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0