
PRELIMINARY
XRT86SH328
IV
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
133
F
IGURE
5. I
LLUSTRATION
OF
THE
F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT86SH328
DEVICE
,
WITH
THE
R
ECEIVE
TUG-3 M
APPER
/VC-4
POH P
ROCESSOR
BLOCK
"
HIGHLIGHTED
"..................................................................................................................... 133
2.6 TRANSMIT STS-1/STS-3 TOH PROCESSOR BLOCK REGISTERS ............................................................ 133
F
IGURE
6. I
LLUSTRATION
OF
THE
F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT86SH328,
WITH
THE
T
RANSMIT
STS-1/STS-3 TOH P
ROCES
-
SOR
B
LOCK
HIGHLIGHTED
............................................................................................................................................ 134
T
ABLE
171: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
3 (A
DDRESS
L
OCATION
= 0
X
0700) ...... 134
T
ABLE
172: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
2 (A
DDRESS
L
OCATION
= 0
X
0701) ..... 135
T
ABLE
173: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
0702) ...... 135
T
ABLE
174: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0703) ...... 136
T
ABLE
175: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
A1 B
YTE
E
RROR
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0717) ......... 138
T
ABLE
176: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
A2 B
YTE
E
RROR
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
071F) ......... 138
T
ABLE
177: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
B1 B
YTE
E
RROR
M
ASK
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0723) 138
T
ABLE
178: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
B2 B
YTE
E
RROR
M
ASK
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0727) 139
T
ABLE
179: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMIT
B2 B
IT
E
RROR
M
ASK
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
072B) ... 139
T
ABLE
180: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- K2 B
YTE
V
ALUE
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
072E) ............ 140
T
ABLE
181: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- K1 B
YTE
V
ALUE
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
072F) ............ 140
T
ABLE
182: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- RDI-L C
ONTROL
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0733) .......................... 140
T
ABLE
183: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- M0M1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0737) ..................... 141
T
ABLE
184: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- S1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
073B) .......................... 141
T
ABLE
185: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- F1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
073F) .......................... 142
T
ABLE
186: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- E1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0743) .......................... 142
T
ABLE
187: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- E2 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0747) .......................... 142
T
ABLE
188: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- J0 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
074B) ........................... 143
T
ABLE
189: T
RANSMIT
STS-1/STS-3 T
RANSPORT
- T
RANSMITTER
J0 B
YTE
C
ONTROL
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
074F) . 143
2.7 TRANSMIT STS-1/STS-3 POH PROCESSOR BLOCK REGISTERS............................................................ 145
F
IGURE
7. I
LLUSTRATION
OF
THE
F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT86SH328,
WITH
THE
T
RANSMIT
STS-1/STS-3 POH P
ROCES
-
SOR
B
LOCK
HIGHLIGHTED
............................................................................................................................................ 145
T
ABLE
190: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
2 (A
DDRESS
L
OCATION
= 0
X
0781) ............... 145
T
ABLE
191: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
0782) ............... 146
T
ABLE
192: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
C
ONTROL
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0783) ................ 147
T
ABLE
193: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMITTER
J1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0793) ................ 148
T
ABLE
194: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
B3 B
YTE
E
RROR
M
ASK
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
0797) .......... 148
T
ABLE
195: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
C2 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
079B) .................... 149
T
ABLE
196: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
G1 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
079F) .................... 149
T
ABLE
197: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
F2 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07A3) ..................... 149
T
ABLE
198: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
H4 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07A7) .................... 150
T
ABLE
199: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
Z3 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07AB) .................... 150
T
ABLE
200: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
Z4 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
N9AF) .................... 150
T
ABLE
201: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
Z5 B
YTE
V
ALUE
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07B3) ..................... 151
T
ABLE
202: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
P
ATH
C
ONTROL
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07B7) ..................... 151
T
ABLE
203: T
RANSMIT
STS-1/STS-3 P
ATH
- SONET P
ATH
J1 C
ONTROL
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07BB) .................. 153
T
ABLE
204: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
A
RBITRARY
H1 P
OINTER
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07BF) ........ 153
T
ABLE
205: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
A
RBITRARY
H2 P
OINTER
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07C3) ........ 154
T
ABLE
206: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
C
URRENT
P
OINTER
B
YTE
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
07C6)
154
T
ABLE
207: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
C
URRENT
P
OINTER
B
YTE
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
07C7)
154
T
ABLE
208: T
RANSMIT
STS-1/STS-3 P
ATH
- RDI-P C
ONTROL
R
EGISTER
- B
YTE
2 (A
DDRESS
L
OCATION
= 0
X
07C9) ..................... 155
T
ABLE
209: T
RANSMIT
STS-1/STS-3 P
ATH
- RDI-P C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
07CA) ..................... 155
T
ABLE
210: T
RANSMIT
STS-1/STS-3 P
ATH
- RDI-P C
ONTROL
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
07CB) ..................... 156
T
ABLE
211: T
RANSMIT
STS-1/STS-3 P
ATH
- S
ERIAL
P
ORT
C
ONTROL
R
EGISTER
(A
DDRESS
L
OCATION
= 0
X
07CF) ......................... 157
T
ABLE
212: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
N
EGATIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCA
-
TION
= 0
X
07D0) ........................................................................................................................................................... 157
T
ABLE
213: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
N
EGATIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCA
-
TION
= 0
X
07D1) ........................................................................................................................................................... 158
T
ABLE
214: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
=
0
X
07D2) ..................................................................................................................................................................... 158
T
ABLE
215: T
RANSMIT
STS-1/STS-3 P
ATH
- T
RANSMIT
P
OSITIVE
P
OINTER
A
DJUSTMENT
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
=
0
X
07D3) ..................................................................................................................................................................... 158
2.8 TRANSMIT TUG-3 MAPPER/VC-4 POH PROCESSOR BLOCK REGISTERS (SDH/TUG-3 APPLICATIONS
ONLY)............................................................................................................................................................ 158
F
IGURE
8. I
LLUSTRATION
OF
THE
F
UNCTIONAL
B
LOCK
D
IAGRAM
OF
THE
XRT86SH328
DEVICE
,
WITH
THE
T
RANSMIT
TUG-3 M
APPER
/VC-
4 POH P
ROCESSOR
BLOCK
"
HIGHLIGHTED
".................................................................................................................. 159
2.9 GLOBAL VT MAPPER BLOCK CONTROL REGISTERS.............................................................................. 159
T
ABLE
216: G
LOBAL
C
ONTROL
- VT-M
APPER
B
LOCK
- VT M
APPER
B
LOCK
C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
0C03) ................. 159