
XRT86SH328
PRELIMINARY
58
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
b.
The STS-1/STS-3 Receive Telecom Bus will expect the RXD_C1J1V1_FP input to pulse high coincident to
whenever the C1 and J1 bytes are being sampled via the RXD_D[7:0] input pins.
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1 - J1 Bytes Only
This selection configures the following.
a.
The Transmit STS-1/STS-3 Telecom Bus Interface to only pulse the TXA_C1J1V1_FP output pin coincident
to whenever the J1 byte is being output via the TXA_D[7:0] output pins.
N
OTE
:
The TXA_C1J1V1_FP output pin will NOT be pulsed high whenever the C1 byte is being output via the
TXA_D[7:0] output pins.
b.
The STS-1/STS-3 Receive Telecom Bus Interface will expect the RXD_C1J1V1_FP input to only pulse high
coincident to whenever the J1 byte is being sampled via the RXD_D[7:0] input pins.
N
OTE
:
The RXD_C1J1V1_FP input pin will NOT be pulsed high whenever the C1 byte is being input via the
RXD_D[7:0] input pins
BIT 2 -
Telecom Bus Parity - ODD Parity Select:
This READ/WRITE bit-field is used to configure the STS-1/STS-3 Telecom Bus Interface to do the following.
a.
In the Transmit (Drop) DirectionThe STS-1/STS-3 Telecom Bus to compute either the EVEN or ODD parity
over the contents of the (1) TxD_D[7:0] output pins, or (2) TxD_D[7:0] output pins, the states of the TxD_PL
and TxD_C1J1 output pins (depending upon user setting for BIT 3).
b.
In the Receive (Add) DirectionReceive STS-1/STS-3 Telecom Bus to compute and verify the EVEN or ODD
parity over the contents of the (1) RxA_D[7:0] input pins, or (2) RxA_D[7:0] input pins, the states of the
RxA_PL and RxA_C1J1 input pins (depending upon user setting for BIT 3).
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0 - Configures Transmit (Drop) Telecom Bus to compute EVEN parity and configures the Receive (Add) Telecom Bus
to verify EVEN parity.
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1 - Configures Transmit (Drop) Telecom Bus to compute ODD parity and configures the Receive (Add) Telecom Bus
to verify ODD parity.
BIT 1 -
Telecom Bus Parity Enable
This READ/WRITE bit-field is used to either enable or disable parity calculation and placement via the TxA_DP output
pin. This bit field also is used to enable or disable parity verification by the Receive Telecom Bus.
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0 - Disables Parity Calculation (on the Transmit Telecom Bus) and Disables Parity Verification (on the Receive
Telecom Bus.
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1 - Enables Parity Calculation and Verification
BIT 0 -
Telecom Bus - Rephase Enable
This READ/WRITE bit-field is used to configure the Receive STS-1/STS-3 Telecom Bus to operate in either the
Rephase ON or Rephase OFF Modes.
If the user configures the Receive STS-1/STS-3 Telecom Bus Interface to operate on the Rephase ON Mode, then the
Receive STS-1/STS-3/STS-1/STS-3 TOH/POH Processor blocks will internally compute the Pointer Bytes, based upon
the data that it receives via the RxD_D[7:0] input pins.
If the user configures the Receive STS-1/STS-3 Telecom Bus Interface to operate in the Rephase OFF Mode, then the
Receive STS-1/STS-3/STS-1/STS-3 TOH/POH Processor blocks will NOT internally compute the Pointer Bytes, based
upon the data that it receives via the RxD_D[7:0] input pins. In this case, the Voyager device will rely upon the signaling
via the Telecom Bus Interface pins (e.g., via the RxD_PL and RxD_C1J1V1_FP pins) in order to compute these pointer
bytes.
N
OTE
:
If the Receive STS-1/STS-3 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the
RxD_C1J1V1_FP input pin), then this feature is unnecessary.
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0 - Configures the Telecom Bus Interface to operate in the Rephase OFF Mode.
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1 - Configures the Telecom Bus Interface to operate in the Rephase ON Mode.