
PRELIMINARY
XRT86SH328
175
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT[7:4] - Reserved
BIT 3 - Receive FIFO Overrun Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Receive FIFO Overrun interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the DS3 Mapper block will generate this interrupt anytime it declares a Receive FIFO
Overrun condition.
`
0 - Indicates that the Receive FIFO Overrun interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Receive FIFO Overrun interrupt has occurred since the last read of this register.
N
OTE
:
The user can obtain the current status of the Receive FIFO Overrun condition by reading the state of BIT 3
(Receive FIFO Overrun Condition) within the DS3 Mapper - Status Register - Byte 0 (Address = 0x0D07).
BIT 2 - Receive FIFO Underrun Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Receive FIFO Underrun interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the DS3 Mapper Block will generate this interrupt anytime it declares a Receive FIFO
Underrun condition.
`
0 - Indicates that the Receive FIFO Underrun interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Receive FIFO Underrun interrupt has occurred since the last read of this register.
N
OTE
:
The user can obtain the current status of the Receive FIFO Underrun condition by reading the state of BIT 2
(Receive FIFO Underrun Condition) within the DS3 Mapper - Status Register - Byte 0 (Address = 0x0D07).
BIT 1 - Transmit FIFO Overrun Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Transmit FIFO Overrun interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the DS3 Mapper block will generate this interrupt anytime it declares a Transmit FIFO
Overrun condition.
`
0 - Indicates that the Transmit FIFO Overrun Interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Transmit FIFO Overrun Interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine the current status of the Transmit FIFO Overrun condition by reading the state of BIT 1
(Transmit FIFO Overrun Condition) within the DS3 Mapper Block - Status Register - Byte 0 (Address =
0x0D07).
BIT 0 - Transmit FIFO Underrun Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Transmit FIFO Underrun interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the DS3 Mapper block will generate this interrupt anytime it declares a Transmit FIFO
Underrun condition.
`
0 - Indicates that the Transmit FIFO Underrun interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Transmit FIFO Underrun interrupt has occurred since the last read of this register.
T
ABLE
231: DS3 M
APPER
B
LOCK
- R
ECEIVE
M
APPER
I
NTERRUPT
S
TATUS
R
EGISTER
- B
YTE
0 (A
DDRESS
=
0
X
0D0B)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Receive
FIFO Over-
run Interrupt
Status
Receive
FIFO Under-
run Interrupt
Status
Transmit
FIFO Over-
run Interrupt
Status
Transmit
FIFO Under-
run Interrupt
Status
R/O
R/O
R/O
R/O
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0