
PRELIMINARY
XRT86SH328
311
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
N
OTE
:
The user must induce a "0 to 1 transition" within Bit 3 (Latch Count) within the "Global VT-Mapper Block - VT
Mapper Block Control Register (Address = 0x0C03) prior to reading out the contents within these bit-fields.
BIT[3:0] - BIP-2 Error Count[11:8]:
These RESET-upon-READ bit-fields, along with those within the VT Mapper Block - Egress Direction - BIP-2 Error
Count Register - Byte 0, presents a 12-bit expression that reflects the number of BIP-2 Errors that the Receive VT-
Mapper Block has detected (within the incoming VT-data-stream) since the last read of this register.
These particular bit-fields are the four most significant bit-fields within this 12-bit expression.
N
OTE
:
The user must induce a "0 to 1 transition" within Bit 3 (Latch Count) within the "Global VT-Mapper Block - VT De-
Mapper Block Control Register (Address = 0x0C03) prior to reading out the contents within these bit-fields
BIT [7:0] - BIP-2 Error Count[7:0]:
These RESET-upon-READ bit-fields, along with those within the VT Mapper Block - Egress Direction - BIP-2 Error
Count Register - Byte 1, presents a 12-bit expression that reflects the number of BIP-2 Errors that the Receive VT-De-
Mapper Block has detected (within the incoming VT-data-stream) since the last read of this register.
These particular bit-fields are the eight least significant bit-fields within this 12-bit expression.
N
OTE
:
The user must induce a "0 to 1 transition" within Bit 3 (Latch Count) within the "Global VT-Mapper Block - VT
Mapper Block Control Register (Address = 0x0C03) prior to reading out the contents within these bit-fields.
BIT [7:4] - VT Payload Pointer Decrement Count[3:0]:
These RESET-upon-READ bit-fields reflect the number of VT Payload Pointer Decrement events that the Receive VT-
De-Mapper block has detected since the last read of this register. The Receive VT-Mapper block will increment the
contents within these bit-fields each time that it detects a VT Payload Pointer Decrement event within the incoming VT
data-stream.
N
OTE
:
The user must induce a "0 to 1 transition" within Bit 3 (Latch Count) within the "Global VT-Mapper Block - VT
Mapper Block Control Register (Address = 0x0C03) prior to reading out the contents within these bit-fields
BIT [3:0] - REI-V Event Count[11:8]:
These RESET-upon-READ bit-fields, along with those within the VT Mapper Block - Egress Direction - REI-V Event
Count Register - Byte 0, presents a 12-bit expression that reflects the number of REI-V Events that the Receive VT-
Mapper Block has detected (within the incoming VT-data-stream) since the last read of this register.
These particular bit-fields are the four most significant bit-fields within this 12-bit expression.
N
OTE
:
The user must induce a "0 to 1 transition" within Bit 3 (Latch Count) within the "Global VT-Mapper Block - VT
Mapper Block Control Register (Address = 0x0C03) prior to reading out the contents within these bit-fields.
T
ABLE
445: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
B
LOCK
- E
GRESS
D
IRECTION
- BIP-2 E
RROR
C
OUNT
R
EGISTER
-
B
YTE
0 (A
DDRESS
= 0
X
ND4B,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIP-2 Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
446: C
HANNEL
C
ONTROL
- VT-D
E
-M
APPER
B
LOCK
- E
GRESS
D
IRECTION
- REI-V E
VENT
C
OUNT
R
EGISTER
-
B
YTE
1 (A
DDRESS
= 0
X
ND4E,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VT-Payload Pointer Decrement Count[3:0]
REI-V Event Count[11:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0