
XRT86SH328
PRELIMINARY
288
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT7 - AUXP Pattern State:
This READ-ONLY register bit indicates whether or not the Receive DS1 Framer block is currently detecting the AUXP
pattern within the incoming DS1 data-stream.
`
0 = Indicates that the Receive DS1 Framer block is NOT currently detecting the AUXP pattern within the incoming
DS1 data-stream.
`
1 = Indicates that the Receive DS1 Framer block is currently detecting the AUXP pattern within the incoming DS1
data-stream.
BIT6 - Change of AUXP State Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Receive DS1 Framer block has declared the Change of
AUXP State Interrupt since the last read of this register. The Receive DS1 Framer block will generate the Change of
AUXP State Interrupt in response to either of the following conditions.
Whenever it begins to detect the AUXP Pattern within the incoming DS1 data-stream, and
Whenever it ceases to detect the AUXP Pattern within the incoming DS1 data-stream.
`
0 = Indicates that the Change of AUXP Status Interrupt has NOT occurred since the last read of this register.
`
1 = Indicates that the Change of AUXP Status Interrupt has occurred since the last read of this register.r
BIT 5 - CRC-4 to Non-CRC-4 Internetworking Status:
BIT 4 - Change of CRC-4 to Non-CRC-4 Internetworking Status:
BIT 3 - Receive Loop-Back Activation Status -Code 0:
This READ-ONLY bit-field indicates whether or not the Receive DS1 Framer block is currently detecting (and flagging)
the Loop-Up (or Loop-Back Activate) code (associated with "Code 0") within the incoming DS1 data-stream.
`
0 = Indicates that the Receive DS1 Framer block is NOT currently detecting (nor flagging) the Loop-Back Activate
Code (associated with "Code 0") within the incoming DS1 data-stream.
`
1 = Indicates that the Receive DS1 Framer block is currently detecting (and flagging) the Loop-Back Activate Code
(associated with "Code 0") within the incoming DS1 data-stream.
N
OTE
:
The Receive DS1/E1 Framer block can be configured to detect three different loop activate/deactivate codes in
parallel. These three (3) codes will be referred to as "Code 0", "Code 1" and "Code 2" within this document. This
particular register applies to "Code 0".
BIT 2 - Receive Loop-Back Deactivation Status - Code 0:
This READ-ONLY bit-field indicates whether or not the Receive DS1 Framer block is currently detecting (and flagging)
the Loop-Down (or Loop-Back Deactivate) code (associated with Code 0) within the incoming DS1 data-stream.
`
0 = Indicates that the Receive DS1 Framer block is NOT currently detecting (nor flagging) the Loop-Back Deactivate
Code (associated with "Code 0") within the incoming DS1 data-stream.
`
1 = Indicates that the Receive DS1 Framer block is currently detecting (and flagging) the Loop-Back Deactivate Code
(associated with "Code 0") within the incoming DS1 data-stream.
BIT 1 - Change of Receive Loop-Back Activation State Interrupt Status - mCode 0:
T
ABLE
426: T1 F
RAMER
I
NTERRUPT
R
EGISTER
- R
ECEIVE
L
OOP
-
BACK
C
ODE
I
NTERRUPT
AND
S
TATUS
R
EGISTER
-
C
ODE
0 (A
DDRESS
= 0
X
NB0A,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
38)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AUXP
Pattern State
Change of
AUXP State
Interrupt
Status
CRC-4 to
Non CRC-4
Inter-net-
working
Status
Change of
CRC-4 to
Non-CRC-4
Inter-net-
working Sta-
tus
Receive
Loop-Back
Activation
Status -Code
0
Receive
Loop-Back
Deactivation
Status -Code
0
Change of
Receive
Loop-Back
Activation
State
Interrupt
Status -Code
0
Change of
Receive
Loop-Back
Deactivation
State I
nterrupt
Status -Code
0
R/O
RUR
R/O
RUR
R/O
R/O
RUR
RUR
0
0
0
0
0
0
0
0