
XRT86SH328
PRELIMINARY
108
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
BIT [7:1] - Unused
BIT 0 - Path Trace Message Unstable Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
Path Trace Message Unstable defect condition. The Receive STS-1 POH Processor block will declare the Path Trace
Message Unstable defect condition, whenever the Path Trace Message Unstable counter reaches the value 8. The
Path Trace Message Unstable counter will be incremented for each time that it receives a Path Trace message that
differs from the previously received message. The Path Trace Unstable counter is cleared to 0 whenever the Receive
STS-1 POH Processor block has received a given Path Trace Message 3 (or 5) consecutive times.
N
OTE
:
Receiving a given Path Trace Message 3 (or 5) consecutive times also sets this bit-field to 0
`
0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the Path Trace Message
Unstable defect.
`
1 - Indicates that the Receive STS-1 POH Processor blolck is currently declaring the Path Trace Message Unstable
defect condition.
BIT 7 - Trace Identification Mismatch (TIM-P) Defect Indicator
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
Path Trace Identification Mismatch (TIM-P) defect condition. The Receive STS-1 POH Processor block will declare the
TIM-P defect condition, when none of the received 64-byte string (received via the J1 byte, within the incoming STS-
1/STS-3 data-stream) matches the expected 64 byte message.The Receive STS-1 POH Processor block will clear the
TIM-P defect condition, when 80% of the received 64 byte string (received via the J1 byte) matches the expected 64
byte message.
`
0 - Indicates that the Receive STS-1 POH Processor block is NOT currently declaring the TIM-P defect condition.
`
1 - Indicates that the Receive STS-1 POH Processor block is currently declaring the TIM-P defect condition.
BIT 6 - C2 Byte (Path Signal Label Byte) Unstable Defect Declared
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH Processor block is currently declaring the
Path Signal Label Byte Unstable defect condition. The Receive STS-1 POH Processor block will declare the C2 (Path
Signal Label Byte) Unstable defect condition, whenever the C2 Byte Unstable counter reaches the value 5. The C2
Byte Unstable counter will be incremented for each time that it receives an SPE with a C2 byte value that differs from
the previously received C2 byte value. The C2 Byte Unstable counter is cleared to 0 whenever the Receive STS-1
POH Processor block has received 3 (or 5) consecutive SPEs that each contains the same C2 byte
T
ABLE
132: R
ECEIVE
STS-1 P
ATH
- C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
0286)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Path Trace
Message
Unstable
Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
T
ABLE
133: R
ECEIVE
STS-1 P
ATH
- SONET R
ECEIVE
POH S
TATUS
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
0287)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIM-P Defect
Declared
C2 Byte
UnstableDe-
fect Declared
UNEQ-PDe-
fectDeclared
PLM-PDe-
fectDeclared
RDI-PDe-
fectDeclared
RDI-P
Unstable-
Condition
LOP-PDe-
fectDeclared
AIS-PDefect-
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0