
XRT86SH328
PRELIMINARY
196
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
REV. P1.0.6
These READ-ONLY bit-fields contain the value of the most recently validated FEAC Code word.
N
OTE
:
These register bits are only active if the Transmit and Receive DS3 Framer blocks have been configured to
operate in the C-bit Parity Framing format.
BIT 0 - Unused:
Bits 7 - 5 - Set to [0, 0, 0]:
`
Please set these three bit-fields to 0 (the default value) for normal operation.
BIT 4 - FEAC Message Valid:
This READ-ONLY bit-field indicates that the FEAC Code word (which resides within the Receive DS3 FEAC Register)
has been validated by the Receive FEAC Controller block. The Receive FEAC Controller block will validate a FEAC
Codeword if it has received this same codeword in 8 out of the last 10 FEAC Messages.
Polled systems can monitor this bit-field when checking for a newly validated FEAC Codeword.
`
0 - Indicates that the FEAC Message (residing in the Receive DS3 FEAC register) is no longer validated.
`
1 - Indicates that the FEAC Message (residing in the Receive DS3 FEAC register) has been validated.
BIT 3 - Receive FEAC Removal Interrupt Enable:
This READ/WRITE bit-field is used to either enable or disable the Receive FEAC Message Removal interrupt. If this
interrupt is enabled, then the Receive DS3 Framer block will generate an interrupt anytime the most recently validated
FEAC Message has been removed. The Receive FEAC Controller will remove a validated FEAC codeword, if it has
received a different codeword in 3 out of the last 10 FEAC Messages.
`
0 - Disables the Receive FEAC Message Removal Interrupt.
`
1 - Enables the Receive FEAC Message Removal Interrupt.
BIT 2 - Receive FEAC Removal Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Receive FEAC Message Removal Interrupt has occurred
since the last read of this register.
`
0 - Indicates that the Receive FEAC Message Removal Interrupt has NOT occurred since the last read of this register.
`
1 - Indicates that the Receive FEAC Message Removal Interrupt has occurred since the last read of this register.
BIT 1 - Receive FEAC Valid Interrupt Enable:
This READ/WRITE bit-field is used to either enable or disable the Receive FEAC Message Validation Interrupt.
If this interrupt is enabled, then the Receive DS3 Framer block will generate an interrupt anytime the Receive
FEAC Controller block has validated a new FEAC Code word.
`
0 - Disables the Receive FEAC Message Validation Interrupt.
`
1 - Enables the Receive FEAC Message Validation Interrupt.
BIT 0 - Receive FEAC Valid Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Receive FEAC Message Validation Interrupt has
occurred since the last read of this register.
`
0 - Indicates that the Receive FEAC Message Validation Interrupt has NOT occurred since the last read of this
T
ABLE
255: DS3 F
RAMER
B
LOCK
- R
ECEIVE
DS3 FEAC I
NTERRUPT
E
NABLE
/S
TATUS
R
EGISTER
(A
DDRESS
=
0
X
0E17)
BIT7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Set to [0, 0, 0]
FEAC Valid
Receive
FEAC
Removal
Interrupt
Enable
Receive
FEAC
Removal
Interrupt
Status
Receive
FEAC Valid
Interrupt
Enable
Receive
FEAC Valid
Interrupt
Status
R/W
R/W
R/W
R/O
R/W
RUR
R/W
RUR
0
0
0
0
0
0
0
0