
PRELIMINARY
XRT86SH328
105
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
`
1 - Configures all 28 of the Egress Direction Transmit DS1/E1 Framer blocks to automatically transmit the DS1/E1
AIS Indicator via the downstream DS1/E1 signals, anytime (and for the duration that) the Receive STS-1/STS-3 TOH
Processor block declares the SF defect condition.
BIT 1 - Unused
BIT 0 - Automatic Transmission of DS1/E1 AIS (via the downstream DS1/E1s) Enable
This READ/WRITE bit-field serves two purposes.It is used to configure each of the 28 Egress Direction Transmit
DS1/E1 Framer blocks to automatically transmit the DS1/E1 AIS Indicator via the downstream DS1/E1 signal, upon
declaration of either the SF, SD, LOS or LOF defect conditions via the Receive STS-1/STS-3 TOH Processor block.
It also is used to configure each of the 28 Egress Direction Transmit DS1/E1 Framer blocks to automatically transmit
the DS1/E1 AIS indicator, via its outbound DS1/E1 signals, upon declaration of the AIS-L defect condition, via the
Receive STS-1/STS-3 TOH Processor block.
`
0 - Does not configure all 28 of the Egress Direction Transmit DS1/E1 Framer blocks to automatically transmit the
DS1/E1 AIS indicator, whenever the Receive STS-1/STS-3 TOH Processor block declares either the LOS, LOF, SD,
SF or AIS-L defect conditions.
`
1 - Configures all 28 of the Egress Direction Transmit DS1/E1 Framer blocks to automatically transmit the DS1/E1
AIS indicator, whenever (and for the duration that) the Receive STS-1/STS-3 TOH Processor block declares either the
LOS, LOF, SD, SF or AIS-L defect conditions.
BIT [7:0] - Receive A1, A2 Byte Error Count Register - MSB Register
This RESET-upon-READ register, along with the Receive STS-1/STS-3 Transport - A1, A2 Byte Error Count Register
- Byte
0 presents a 16-bit representation of the total number of A1 and A2 byte errors that the Receive STS-1/STS-3 TOH
Processor block has detected (within the incoming STS-1/STS-3 data-stream) since the last read of this register.
N
OTE
:
This register contains the MSB (Most Significant Byte) of this 16-bit expression.
BIT [7:0] - Receive A1, A2 Byte Error Count Register - LSB Register
This RESET-upon-READ register, along with the Receive STS-1/STS-3 Transport - A1, A2 Byte Error Count Register
- Byte 1 presents a 16-bit representation of the total number of A1 and A2 byte errors that the Receive STS-1/STS-3
TOH Processor block has detected (within the incoming STS-1/STS-3 data-stream) since the last read of this register.
N
OTE
:
This register contains the LSB (Least Significant Byte) of this 16-bit expression.
2.4
RECEIVE STS-1 POH PROCESSOR BLOCK REGISTERS
The register map for the Receive STS-1 POH Processor Block is presented in the Table below. Additionally, a
detailed description of each of the Receive STS-1/STS-3 POH Processor block registers is presented below.
T
ABLE
128: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- A1, A2 B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
1 (A
DDRESS
L
OCATION
= 0
X
026E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive A1, A2 Byte Error Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
T
ABLE
129: R
ECEIVE
STS-1/STS-3 T
RANSPORT
- A1, A2 B
YTE
E
RROR
C
OUNT
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
= 0
X
026F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive A1, A2 Byte Error Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0