
PRELIMINARY
XRT86SH328
327
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
These three READ/WRITE bit-field permits the user to specify the value that the VT-Mapper block will transmit, within
the RDI-V bit-fields of the K4 byte (within each outbound VT-frame) whenever (and for the duration that) the
corresponding VT-De-Mapper block detects and declare the UNEQ-V defect condition.
N
OTE
:
In order to enable this feature, the user must set Bit 0 (Transmit RDI-V upon UNEQ-V) within this register to "1".
Bit 0 - Transmit RDI-V upon UNEQ-V
This READ/WRITE bit-field permits the user to configure the VT-Mapper block to automatically transmit the RDI Code
(as configured in Bits 3 through 1 - within this register) towards the remote VT PTE whenever (and for the duration that)
the corresponding VT-De-Mapper block declares the UNEQ-V defect condition.
`
0 - Configures the VT-Mapper block to NOT automatically transmit the RDI Code (via the K4 byte) whenever (and for
the duration that) the corresponding VT-De-Mapper block declares the UNEQ-V defect condition.
`
1 - Configures the VT-Mapper block to automatically transmit the RDI Code (via the K4 byte) whenever (and for the
duration that) the corresponding VT-De-Mapper block declares the UNEQ-V defect condition.
Bits 7 - 5 - LOP-V RDI Code[2:0]:
These three READ/WRITE bit-field permits the user to specify the value that the VT-Mapper block will transmit, within
the RDI-V bit-fields of the K4 byte (within each outbound VT-frame) whenever (and for the duration that) the
corresponding VT-De-Mapper block detects and declare the LOP-V defect condition.
N
OTE
:
In order to enable this feature, the user must set Bit 0 (Transmit RDI-V upon LOP-V) within this register to "1".
Bit 4 - Transmit RDI-V upon LOP-V
This READ/WRITE bit-field permits the user to configure the VT-Mapper block to automatically transmit the RDI Code
(as configured in Bits 3 through 1 - within this register) towards the remote VT PTE whenever (and for the duration that)
the corresponding VT-De-Mapper block declares the LOP-V defect condition.
`
0 - Configures the VT-Mapper block to NOT automatically transmit the RDI Code (via the K4 byte) whenever (and for
the duration that) the corresponding VT-De-Mapper block declares the LOP-V defect condition.
`
1 - Configures the VT-Mapper block to automatically transmit the RDI Code (via the K4 byte) whenever (and for the
duration that) the corresponding VT-De-Mapper block declares the LOP-V defect condition.
Bits 3 - 1 - AIS-V RDI Code[2:0]:
These three READ/WRITE bit-field permits the user to specify the value that the VT-Mapper block will transmit, within
the RDI-V bit-fields of the K4 byte (within each outbound VT-frame) whenever (and for the duration that) the
corresponding VT-De-Mapper block detects and declare the AIS-V defect condition.
N
OTE
:
In order to enable this feature, the user must set Bit 0 (Transmit RDI-V upon AIS-V) within this register to "1".
Bit 0 - Transmit RDI-V upon AIS-V
This READ/WRITE bit-field permits the user to configure the VT-Mapper block to automatically transmit the RDI Code
(as configured in Bits 3 through 1 - within this register) towards the remote VT PTE whenever (and for the duration that)
the corresponding VT-De-Mapper block declares the AIS-V defect condition.
`
0 - Configures the VT-Mapper block to NOT automatically transmit the RDI Code (via the K4 byte) whenever (and for
the duration that) the corresponding VT-De-Mapper block declares the AIS-V defect condition.
`
1 - Configures the VT-Mapper block to automatically transmit the RDI Code (via the K4 byte) whenever (and for the
duration that) the corresponding VT-De-Mapper block declares the AIS-V defect condition.
T
ABLE
466: C
HANNEL
C
ONTROL
- VT-M
APPER
B
LOCK
- I
NGRESS
D
IRECTION
- T
RANSMIT
RDI-V C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
= 0
X
ND86,
WHERE
N
RANGES
IN
VALUE
FROM
0
X
01
TO
0
X
1C)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
LOP-V RDI CODE[2:0]
Transmit
RDI-V upon
LOP-V
AIS-V RDI CODE[2:0]
Transmit
RDI-V upon
AIS-V
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0