
PRELIMINARY
XRT86SH328
83
REV. P1.0.6
28-CHANNEL DS1/E1 FRAMER/LIU WITH DS3 MUX & VT-MAPPER - SONET APPLICATIONS
BIT 7 - Change of Signal Failure (SF) Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of Signal Failure (SF) Defect Condition
Interrupt. If this interrupt is enabled, then the XRT86SH328 will generate an interrupt in response to any of the following
events.
Whenever the Receive STS-1/STS-3 TOH Processor block declares the SF defect condition.
Whenever the Receive STS-1/STS-3 TOH Processor block clears the SF defect condition.
`
0 - Disables the Change of SF Defect Condition Interrupt.
`
1 - Enables the Change of SF Defect Condition Interrupt.
BIT 6 - Change of Signal Degrade (SD) Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of Signal Degrade (SD) Defect Condition
Interrupt. If this interrupt is enabled, then the XRT86SH328 will generate an interrupt in response to either of the
following events.
Whenever the Receive STS-1/STS-3 TOH Processor blolck declares the SD defect condition.
Whenever the Receive STS-1/STS-3 TOH Processor block clears the SD defect condition.
`
0 - Disables the Change of SD Defect Condition Interrupt.
`
1 - Enables the Change of SD Defect Condition Interrupt.
BIT 5 - Detection of REI-L (Line - Remote Error Indicator) Event Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of REI-L Event interrupt. If this interrupt is
enabled, then the XRT86SH328 will generate an interrupt anytime the Receive STS-1/STS-3 TOH Processor block
detects an REI-L condition within the incoming STS-1/STS-3 data-stream.
`
0 - Disables the Detection of REI-L Event Interrupt.
`
1 - Enables the Detection of REI-L Event Interrupt.
BIT 4 - Detection of B2 Byte Error Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Detection of B2 Byte Error Interrupt. If this interrupt
is enabled, then the XRT86SH328 will generate an interrupt anytime the Receive STS-1/STS-3 TOH Processor block
detects a B2 byte error within the incoming STS-1/STS-3 data-stream.
`
0 - Disables the Detection of B2 Byte Error Interrupt.
`
1 - Enables the Detection of B2 Byte Error Interrupt.
BIT 3 - Detection of B1 Byte Error Interrupt Enable:
This READ/WRITE bit-field is used to either enable or disable the Detection of B1 Byte Error Interrupt. If this interrupt
is enabled, then the XRT86SH328 will generate an interrupt anytime the Receive STS-1/STS-3 TOH Processor block
detects a B1 byte error within the incoming STS-1/STS-3 data-stream.
`
0 - Disables the Detection of B1 Byte Error Interrupt.
`
1 - Enables the Detection of B1 Byte Error Interrupt.
BIT 2 - Change of Loss of Frame (LOF) Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change of LOF Defect Condition interrupt. If this
T
ABLE
81: R
ECEIVE
STS-1/STS-3 T
RANSPORT
I
NTERRUPT
S
TATUS
R
EGISTER
- B
YTE
0 (A
DDRESS
L
OCATION
=
0
X
020F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF Defect-
Condition
Interrupt
Enable
Change of
SD Defect
Condition
Interrupt
Enable
Detection of
REI-L Event
Interrupt
Enable
Detection of
B2 Byte
Error Inter-
rupt Enable
Detection of
B1 Byte
Error Inter-
rupt Enable
Change of
LOF Defect
Condition
Interrupt
Enable
Change of
SEF Defect
Condition
Interrupt
Enable
Change of
LOS Defect
Condition
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0